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[QUESTION] Why do component instantiations create dependencies on entity/module implementations? #1126

@std-max

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@std-max

Hi VUnit team!

I've got a question regarding how VUnit resolves dependencies in the presence of component instantiations in VHDL.

Let's say I have two entities A and B.
A instantiates a component B.
B instantiates a component A.
This circular dependency should not necessarily be problematic if the component declarations are properly defined in packages or in architecture declaration regions. However during compilation, it seems that component instantiations create circular dependencies due to the actual component/entity matching implementation.

From my understanding this implies that VUnit tries to resolve the instantiation by locating a matching entity, which can affect the topological sort of the files. I am curious about the rationale behind this behavior since it prevents me from compiling my source code (in fact I found a way to compile without changing source code with --test-prio=ordered).
If this behavior is something that can or should be adjusted, I would be happy to look into it and possibly contribute a PR.

Thank you!

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