Different behavior between GHDL/ModelSim and NVC for VHDL file access

[jorkrohn]

I have a simulation model written in VHDL that reads an input file called design.dat. Note that this model only specifies "design.dat" in the VHDL code without any path. This is a generated file so I want to avoid changing it.

For the simulation to run correctly I have added a pre simulation hook (pre_config) that copies design.dat to the simulation output path given by the simulator_output_path argument of pre_config. This works fine in GHDL and ModelSim simulations.

However, for NVC I need to copy the file to the directory I'm standing in when running run.py

I'm using version 5.0.0.dev6

[LarsAsplund]

That sound like a bug. I will investigate.