feat: release and resume inference runtime - #56
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Add a reversible scheduler lifecycle that drops scheduler-owned KV storage, decode workspace, and CUDA graph state while retaining shared model weights and policy version. Expose the lifecycle through inference and rollout APIs, clear cached rollout tensors, and add single-GPU memory/parity benchmarking.
Capture five release/resume cycles for the AstrAI 1B BF16 preset at 2K, 8K, and 32K context bounds, including raw memory, latency, and greedy-parity data from the implementation commit.
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Summary
resume()and restart an async loop only when it was previously runningInferenceEngine,RolloutGenerator, andRolloutRunner, including rollout tensor-cache cleanupNVIDIA L20 benchmark
AstrAI 1B, BF16, batch 4, prompt 128, four greedy decode tokens, five cycles per cell:
Implementation commit:
5900c786322b522162af0bef0674464806f1628a.A separate three-L20 stability soak ran 100 cycles per context with the tiny deterministic preset:
All 300/300 post-resume greedy outputs matched. The tiny-preset footprint is stability evidence and is not directly comparable to the AstrAI-1B memory table.
Validation
docs/benchmarks/811bc775: comparison cell valid; 53 Draft/system-path tests passedInfraSWE scoring is diagnostic and unsealed. CUDA graphs were disabled to isolate scheduler-owned state. The source-mounted runtime used established extension fallbacks, so this PR makes a lifecycle/allocation claim rather than a kernel-throughput claim.