hw/arm/xlnx-versal: fix Versal2 VxWorks CPU boot#45
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shivkd
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I'm being a bit nitpicky and pedantic here, but vxworks does not enable PSCI - it uses PSCI to enable the secondary cpu cores. PSCI is an interface that is implemented by the ATF. I think it is important to understand the distinction here. So in actuality, PSCI has nothing to do with this change, except that vxworks bails out of secondary cpu initialization due to a device tree parsing issue before attempting to enable the secondary cpus via PSCI (which is functioning properly without this change) Besides that the change looks good. Thanks for finding and fixing the issue! |
ho28
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ho28
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Line length on the commit message is long.
But i see you characterized the issue correctly here - with the cpu node @ change, vxworks is able to identify the secondary cpus and successfully attempt to power them on using PSCI CPU_ON command.
I would mention that it is not a requirement to keep the CPU node address value aligned with their reg values, just that this is what vxworks expects. Linux properly parses the mpidr values from reg property even with linear cpu node address values, so this is a vxworks specific fix
Fair enough, youre right it doesnt enable PSCI, made the comment factually correct now. |
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| { | ||
| ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
| size_t idx = cluster_idx * map->num_core + core_idx; | ||
| uint32_t affinity = arm_cpu_mp_affinity(arm_cpu) & ARM64_AFFINITY_MASK; |
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i think this should actually be uint64_t
VxWorks requires the Versal2 compatible string and looks up secondary CPU nodes using MPIDR CPU IDs. Add the amd,versal2 compatible string for the Versal2 machine and generate CPU node addresses from the MPIDR affinity value instead of the linear CPU index. This keeps CPU node names aligned with their reg values, for example cpu@100 with reg = <0x100>. With this change, VxWorks can match the Versal2 DTB, discover secondary CPU nodes, reach the PSCI CPU_ON path, and bring all application CPUs online. Signed-off-by: shivkd <shiveshkd@gmail.com>
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VxWorks requires the QEMU generated Versal2 DTB to expose the expected board compatible string and CPU node number to boot Vxworks and turn on the secondary CPUs. This change adds the amd,versal2 compatible string for amd-versal2-virt and updates CPU DT node generation to use the MPIDR affinity value for the CPU node unit address.
Previously, QEMU generated CPU node names from a linear CPU index while setting reg to the MPIDR affinity value, producing nodes such as cpu@1 with reg = <0x100>. VxWorks looks up secondary CPU nodes using the MPIDR-based CPU ID, for example /cpus/cpu@100. Since cpu@100 did not exist, vxFdtPathOffset() failed and the CPU enable path returned before reaching vxPsciCpuOn() / PSCI CPU_ON. Using the MPIDR affinity value for both the unit address and reg produces nodes such as cpu@100 with reg = <0x100>. With this change, VxWorks discovers the secondary CPU nodes correctly and brings all 8 application CPUs online on amd-versal2-virt. Tested by booting VxWorks 26.03 SMP on amd-versal2-virt and confirming vxCpuEnabledGet() returns 0xff.