feat: stm32u5xx independent watchdog (iwdg)

[sanyaswee]

Pull Request Overview

This pull request implements IWDG (Independent Watchdog) on stm32u5xx chips and enables it on nucleo_u545re_q

Testing Strategy

This pull request was tested by flashing the new kernel and installing the applications on it

TODO or Help Wanted

The main concern regarding my implementation is that the watchdog reboots the board not only when the processor freezes, but also when it "sleeps" if no applications are running. For example, if we install only c_hello app, it would infinitly print "Hello World", because the program finishes and the OS sleeps. But if we install many apps, for example c_hello and blink, the watchdog would work as intended, and c_hello would print its message only once.

If I identified the issue source correctly, it comes from the WatchDog trait, specifically this function:

/// Suspends the watchdog timer. After calling this the timer should not
/// fire until after `tickle()` has been called. This function is called
/// before sleeping.
fn suspend(&self) {}

The OS expects us to temporary turn off the timer, however I did not find out how to do it. On the datasheet the status registers are read only, and the STM forum says it is not possible to stop it after enabling

To address this I've marked the lines that should be commented to disable the watchdog if needed, but I don't think that is the best approach

Documentation Updated

• Updated the relevant files in /docs, or no updates are required.

Formatting

• Ran make prepush.

AI Use

• The PR description details my use of AI in the production of the
  code in this PR, if any, and I have manually checked and
  personally certify the entire contents of this PR.

[sanyaswee]

I have an idea about a workaround for sleep reboot, what if instead of suspending it we reconfigure the timer to make it as slow as possible?

The default config is the divider of 32 and 1000 as a reload value, which gives us 1 second before the reboot. According to the datasheet, the maximum divider is 1024, and the maximum 12 bit integer is 4095. If we configure it with these values:
32 kHz / 1024 = 31.25 Hz => 31.25 ticks per second. 4095 / 31.25 = 131s

131s is still a small value, but what if we make the system wake up, tickle, and go back to sleep every 130s? And after "real" wake up we would reconfigure the watchdog back to normal values?

I have no idea how to implement it though, the sleep mode and tickle calls are probably configured somewhere in the kernel, and changing that logic may break other boards that support watchdog suspending

[sanyaswee]

I have found a chip-specific sleep function for the stm32u5xx, it is located in chips/stm32u5xx/src/chip.rs

fn sleep(&self) {
        unsafe {
            cortexm33::scb::unset_sleepdeep();
            cortexm33::support::wfi();
        }
    }

For a workaround we need to schedule an interrupt in 130s, but the systick would overflow much faster, so we need to use something like RTC, which is not implemented yet (Nicolas is working on it now)

[genan2003]

I have found a chip-specific sleep function for the stm32u5xx, it is located in chips/stm32u5xx/src/chip.rs

fn sleep(&self) {
        unsafe {
            cortexm33::scb::unset_sleepdeep();
            cortexm33::support::wfi();
        }
    }

For a workaround we need to schedule an interrupt in 130s, but the systick would overflow much faster, so we need to use something like RTC, which is not implemented yet (Nicolas is working on it now)

Some updates on this?

[sanyaswee]

I have found a chip-specific sleep function for the stm32u5xx, it is located in chips/stm32u5xx/src/chip.rs

fn sleep(&self) {
        unsafe {
            cortexm33::scb::unset_sleepdeep();
            cortexm33::support::wfi();
        }
    }

For a workaround we need to schedule an interrupt in 130s, but the systick would overflow much faster, so we need to use something like RTC, which is not implemented yet (Nicolas is working on it now)

Some updates on this?

Waiting for RTC to be finished

[genan2003]

I have found a chip-specific sleep function for the stm32u5xx, it is located in chips/stm32u5xx/src/chip.rs

fn sleep(&self) {
        unsafe {
            cortexm33::scb::unset_sleepdeep();
            cortexm33::support::wfi();
        }
    }

For a workaround we need to schedule an interrupt in 130s, but the systick would overflow much faster, so we need to use something like RTC, which is not implemented yet (Nicolas is working on it now)

Some updates on this?

Waiting for RTC to be finished

Alright, when all the stuff is finished, please ping me.