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Esp32 c3 led pwm #8

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Esp32 c3 led pwm #8

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cf63e75
initial commit
CosminGGeorgescu Oct 28, 2022
eeca123
finished Timers part + cleaner code
CosminGGeorgescu Nov 4, 2022
3e89311
finished Pwm part + board declaration
CosminGGeorgescu Nov 15, 2022
ec75dcb
much cleaner implementation
CosminGGeorgescu Nov 18, 2022
e2f6e4d
DutyCycle enum clarifications
CosminGGeorgescu Dec 20, 2022
8b1021e
max_frq_hz trait method implemented
CosminGGeorgescu Jan 9, 2023
1e8cb38
max_duty_cycle method implemented
CosminGGeorgescu Jan 13, 2023
719cd38
rising anew
CosminGGeorgescu Jan 17, 2023
780018d
added RcFast CPU clock + prescaler option RcFast/Xtal
CosminGGeorgescu Jan 17, 2023
93ec607
get_cpu_clock
CosminGGeorgescu Jan 18, 2023
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1 change: 1 addition & 0 deletions boards/esp32-c3-devkitM-1/src/main.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -148,6 +148,7 @@ unsafe fn setup() -> (
peripherals.rtc_cntl.disable_super_wdt();
peripherals.sysreg.disable_timg0();
peripherals.sysreg.enable_timg0();
peripherals.sysreg.enable_ledc();

peripherals
.sysreg
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8 changes: 8 additions & 0 deletions chips/esp32-c3/src/chip.rs
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Expand Up @@ -13,6 +13,7 @@ use rv32i::syscall::SysCall;

use crate::intc::{Intc, IntcRegisters};
use crate::interrupts;
use crate::led_pwm;
use crate::sysreg;
use crate::timg;

Expand All @@ -35,6 +36,7 @@ pub struct Esp32C3DefaultPeripherals<'a> {
pub gpio: esp32::gpio::Port<'a>,
pub rtc_cntl: esp32::rtc_cntl::RtcCntl,
pub sysreg: sysreg::SysReg,
pub led_pwm: led_pwm::LedPwm,
}

impl<'a> Esp32C3DefaultPeripherals<'a> {
Expand All @@ -46,6 +48,7 @@ impl<'a> Esp32C3DefaultPeripherals<'a> {
gpio: esp32::gpio::Port::new(),
rtc_cntl: esp32::rtc_cntl::RtcCntl::new(esp32::rtc_cntl::RTC_CNTL_BASE),
sysreg: sysreg::SysReg::new(),
led_pwm: led_pwm::LedPwm::new(),
}
}
}
Expand All @@ -65,6 +68,11 @@ impl<'a> InterruptService<()> for Esp32C3DefaultPeripherals<'a> {
interrupts::IRQ_GPIO | interrupts::IRQ_GPIO_NMI => {
self.gpio.handle_interrupt();
}
interrupts::IRQ_LEDC => {
//handler is unimplemented yet
//not sure exactly what to do :)
self.led_pwm.handle_interrupt();

@alexandruradovici alexandruradovici Jan 14, 2023

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What is the purpose of the PWM interrupt?

@CosminGGeorgescu CosminGGeorgescu Jan 16, 2023

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It is triggered either when a timer counter overflows for a set number of times, when a fade has finished or when a timer counter has reached it's max value.

}
_ => return false,
}
true
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7 changes: 5 additions & 2 deletions chips/esp32-c3/src/intc.rs
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Expand Up @@ -16,16 +16,18 @@ register_structs! {
(0x048 => _reserved1),
(0x054 => uart0_intr_map: ReadWrite<u32>),
(0x058 => _reserved2),
(0x05C => ledc_intr_map: ReadWrite<u32>),
(0x060 => _reserved3),
(0x080 => timg0_intr_map: ReadWrite<u32>),
(0x084 => timg1_intr_map: ReadWrite<u32>),
(0x088 => _reserved3),
(0x088 => _reserved4),
(0x0f8 => status: [ReadWrite<u32>; 2]),
(0x100 => clk_en: ReadWrite<u32>),
(0x104 => enable: ReadWrite<u32, INT::Register>),
(0x108 => type_reg: ReadWrite<u32, INT::Register>),
(0x10C => clear: ReadWrite<u32, INT::Register>),
(0x110 => eip: ReadWrite<u32, INT::Register>),
(0x114 => _reserved4),
(0x114 => _reserved5),
(0x118 => priority: [ReadWrite<u32, PRIORITY::Register>; 31]),
(0x194 => thresh: ReadWrite<u32, THRESH::Register>),
(0x198 => @END),
Expand Down Expand Up @@ -71,6 +73,7 @@ impl Intc {
/// In Tock we map them ourselves so we don't need to call into the ROM.
pub fn map_interrupts(&self) {
self.registers.uart0_intr_map.set(interrupts::IRQ_UART0);
self.registers.ledc_intr_map.set(interrupts::IRQ_LEDC);
self.registers.timg0_intr_map.set(interrupts::IRQ_TIMER1);
self.registers.timg1_intr_map.set(interrupts::IRQ_TIMER2);
self.registers
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