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Simplify AIE Dtrace CT file generation for bandwidth metrics#40

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jvillarre merged 4 commits intoXilinx:masterfrom
jyothees99:simplify-dtrace-ct-bandwidth
Apr 16, 2026
Merged

Simplify AIE Dtrace CT file generation for bandwidth metrics#40
jvillarre merged 4 commits intoXilinx:masterfrom
jyothees99:simplify-dtrace-ct-bandwidth

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This change simplifies the CT file generation for bandwidth monitoring:

  • Add self-contained CT generation that configures hardware directly via write_reg commands in the begin block (stream switch ports and perf counters)
  • Remove dependency on setMetricsSettings() - return early after nop.elf
  • Fix VE2 shim tile DMA port mappings:
    • S2MM ch0: master South1, port index 3
    • S2MM ch1: master South3, port index 5
    • MM2S ch0: slave South3, port index 5
    • MM2S ch1: slave South7, port index 9
  • Fix performance counter control register addresses:
    • Performance_Ctrl0 at 0x00031000 for counters 0,1
    • Performance_Ctrl2 at 0x0003100C for counters 2,3
  • Fix PORT_RUNNING event numbers for aie2ps shim tiles:
    • Port_Running_0 = 134 (0x86)
    • Port_Running_1 = 138 (0x8A)
    • Port_Running_2 = 142 (0x8E)
    • Port_Running_3 = 146 (0x92)
  • Use relative column indices for hardware configuration
  • Generate per-UC grouped counter metadata (compatible with vaianalyze)
  • Remove inline comments from write_reg/read_reg actions

Post-processing filters bandwidth data by metric type:

  • read_bandwidth: S2MM counters (0, 1)
  • write_bandwidth: MM2S counters (2, 3)
  • ddr_bandwidth: all 4 counters

Made-with: Cursor

This change simplifies the CT file generation for bandwidth monitoring:

- Add self-contained CT generation that configures hardware directly via
  write_reg commands in the begin block (stream switch ports and perf counters)
- Remove dependency on setMetricsSettings() - return early after nop.elf
- Fix VE2 shim tile DMA port mappings:
  - S2MM ch0: master South1, port index 3
  - S2MM ch1: master South3, port index 5
  - MM2S ch0: slave South3, port index 5
  - MM2S ch1: slave South7, port index 9
- Fix performance counter control register addresses:
  - Performance_Ctrl0 at 0x00031000 for counters 0,1
  - Performance_Ctrl2 at 0x0003100C for counters 2,3
- Fix PORT_RUNNING event numbers for aie2ps shim tiles:
  - Port_Running_0 = 134 (0x86)
  - Port_Running_1 = 138 (0x8A)
  - Port_Running_2 = 142 (0x8E)
  - Port_Running_3 = 146 (0x92)
- Use relative column indices for hardware configuration
- Generate per-UC grouped counter metadata (compatible with vaianalyze)
- Remove inline comments from write_reg/read_reg actions

Post-processing filters bandwidth data by metric type:
- read_bandwidth: S2MM counters (0, 1)
- write_bandwidth: MM2S counters (2, 3)
- ddr_bandwidth: all 4 counters

Made-with: Cursor
Add write_reg commands to reset performance counters 0-3 to zero
before configuring the counter control registers. This ensures
counters start from a known state for accurate bandwidth measurement.

Counter addresses (aie2ps_pl_module):
- Performance_Counter0: 0x00031020
- Performance_Counter1: 0x00031024
- Performance_Counter2: 0x00031028
- Performance_Counter3: 0x0003102C

Made-with: Cursor
Improve code readability by using more descriptive variable names:
- asmFiles -> asmFileInfoList
- asmFile -> asmFileInfo

The struct ASMFileInfo name remains unchanged.

Made-with: Cursor
@jyothees99 jyothees99 requested a review from jvillarre April 14, 2026 15:12
CT file handles all hardware configuration via write_reg commands
in the begin block. No need to submit nop.elf or call setMetricsSettings
in updateDevice. The original code is preserved for potential fallback
flow in the future.

Made-with: Cursor
@jvillarre jvillarre merged commit 866771e into Xilinx:master Apr 16, 2026
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3 participants