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brcc.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;
; This file is licensed under the Apache License v2.0 with LLVM Exceptions.
; See https://llvm.org/LICENSE.txt for license information.
; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
;
; (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
; RUN: llc -mtriple=aie2 --issue-limit=8 < %s | FileCheck %s
define i32 @br_i32(i32 %a, i32 %b, i32 %v, i32* nocapture writeonly %c) {
; CHECK-LABEL: br_i32:
; CHECK: .p2align 4
; CHECK-NEXT: // %bb.0: // %entry
; CHECK-NEXT: nopa ; nopb ; geu r1, r2, r1; nopm ; nops
; CHECK-NEXT: jnz r1, #.LBB0_2
; CHECK-NEXT: nop // Delay Slot 5
; CHECK-NEXT: nop // Delay Slot 4
; CHECK-NEXT: nop // Delay Slot 3
; CHECK-NEXT: nop // Delay Slot 2
; CHECK-NEXT: mov r0, r3 // Delay Slot 1
; CHECK-NEXT: // %bb.1: // %if.then
; CHECK-NEXT: nopb ; nopa ; st r0, [p0, #0]; nopxm ; nopv
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_2: // %if.end
; CHECK-NEXT: nopa ; ret lr
; CHECK-NEXT: nop // Delay Slot 5
; CHECK-NEXT: nop // Delay Slot 4
; CHECK-NEXT: nop // Delay Slot 3
; CHECK-NEXT: nop // Delay Slot 2
; CHECK-NEXT: nop // Delay Slot 1
entry:
%cmp = icmp ugt i32 %a, %b
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
store i32 %v, i32* %c, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret i32 %v
}
; if.end should be moved to the end to allow fall-through.
define i32 @br_i32_reverse(i32 %a, i32 %b, i32 %v, i32* nocapture writeonly %c) {
; CHECK-LABEL: br_i32_reverse:
; CHECK: .p2align 4
; CHECK-NEXT: // %bb.0: // %entry
; CHECK-NEXT: nopa ; nopb ; ltu r1, r2, r1; nopm ; nops
; CHECK-NEXT: jz r1, #.LBB1_2
; CHECK-NEXT: nop // Delay Slot 5
; CHECK-NEXT: nop // Delay Slot 4
; CHECK-NEXT: nop // Delay Slot 3
; CHECK-NEXT: nop // Delay Slot 2
; CHECK-NEXT: mov r0, r3 // Delay Slot 1
; CHECK-NEXT: // %bb.1: // %if.then
; CHECK-NEXT: nopb ; nopa ; st r0, [p0, #0]; nopxm ; nopv
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB1_2: // %if.end
; CHECK-NEXT: nopa ; ret lr
; CHECK-NEXT: nop // Delay Slot 5
; CHECK-NEXT: nop // Delay Slot 4
; CHECK-NEXT: nop // Delay Slot 3
; CHECK-NEXT: nop // Delay Slot 2
; CHECK-NEXT: nop // Delay Slot 1
entry:
%cmp = icmp ugt i32 %a, %b
br i1 %cmp, label %if.then, label %if.end
if.end: ; preds = %if.then, %entry
ret i32 %v
if.then: ; preds = %entry
store i32 %v, i32* %c, align 4
br label %if.end
}
define i32 @br_diamond(i32 %a, i32 %b, i32 %v, i32* nocapture writeonly %c) {
; CHECK-LABEL: br_diamond:
; CHECK: .p2align 4
; CHECK-NEXT: // %bb.0: // %entry
; CHECK-NEXT: nopa ; nopb ; geu r1, r2, r1; nopm ; nops
; CHECK-NEXT: jnz r1, #.LBB2_2
; CHECK-NEXT: nop // Delay Slot 5
; CHECK-NEXT: nop // Delay Slot 4
; CHECK-NEXT: nop // Delay Slot 3
; CHECK-NEXT: nop // Delay Slot 2
; CHECK-NEXT: mov r0, r3 // Delay Slot 1
; CHECK-NEXT: // %bb.1: // %if.then
; CHECK-NEXT: ret lr
; CHECK-NEXT: nop // Delay Slot 5
; CHECK-NEXT: nop // Delay Slot 4
; CHECK-NEXT: nop // Delay Slot 3
; CHECK-NEXT: st r0, [p0, #0] // Delay Slot 2
; CHECK-NEXT: nop // Delay Slot 1
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB2_2: // %if.else
; CHECK-NEXT: nopb ; nopa ; nops ; ret lr ; nopm ; nopv
; CHECK-NEXT: nopx // Delay Slot 5
; CHECK-NEXT: nop // Delay Slot 4
; CHECK-NEXT: mova r1, #0 // Delay Slot 3
; CHECK-NEXT: st r1, [p0, #0] // Delay Slot 2
; CHECK-NEXT: nop // Delay Slot 1
entry:
%cmp = icmp ugt i32 %a, %b
br i1 %cmp, label %if.then, label %if.else
if.then: ; preds = %entry
store i32 %v, i32* %c, align 4
br label %if.end
if.else: ; preds = %entry
store i32 0, i32* %c, align 4
br label %if.end
if.end: ; preds = %if.then, %if.else
ret i32 %v
}
; Because of the call to @foo, r16 is spilled and reloaded in the end
; basic block. There is a single BB with a ret instruciton, contrary
; to the previous example.
define i32 @br_diamond_complex_end(i32 %a, i32 %b, i32 %v, i32* nocapture writeonly %c) {
; CHECK-LABEL: br_diamond_complex_end:
; CHECK: .p2align 4
; CHECK-NEXT: // %bb.0: // %entry
; CHECK-NEXT: nopa ; nopb ; geu r0, r2, r1
; CHECK-NEXT: jnz r0, #.LBB3_2
; CHECK-NEXT: nop // Delay Slot 5
; CHECK-NEXT: paddb [sp], #32 // Delay Slot 4
; CHECK-NEXT: st r16, [sp, #-32] // 4-byte Folded Spill Delay Slot 3
; CHECK-NEXT: st lr, [sp, #-28] // 4-byte Folded Spill Delay Slot 2
; CHECK-NEXT: mov r16, r3 // Delay Slot 1
; CHECK-NEXT: // %bb.1: // %if.then
; CHECK-NEXT: nopb ; nopa ; nops ; j #.LBB3_3; nopv
; CHECK-NEXT: nopa ; nopx // Delay Slot 5
; CHECK-NEXT: nop // Delay Slot 4
; CHECK-NEXT: nop // Delay Slot 3
; CHECK-NEXT: st r16, [p0, #0] // Delay Slot 2
; CHECK-NEXT: nop // Delay Slot 1
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB3_2: // %if.else
; CHECK-NEXT: nopb ; nopa ; nops ; jl #foo; nopv
; CHECK-NEXT: nopa ; nopx // Delay Slot 5
; CHECK-NEXT: nop // Delay Slot 4
; CHECK-NEXT: nop // Delay Slot 3
; CHECK-NEXT: nop // Delay Slot 2
; CHECK-NEXT: mov r0, r16 // Delay Slot 1
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB3_3: // %if.end
; CHECK-NEXT: nopb ; lda lr, [sp, #-28]; nops ; nopxm ; nopv // 4-byte Folded Reload
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: lda r16, [sp, #-32] // 4-byte Folded Reload
; CHECK-NEXT: ret lr
; CHECK-NEXT: nop // Delay Slot 5
; CHECK-NEXT: nop // Delay Slot 4
; CHECK-NEXT: nop // Delay Slot 3
; CHECK-NEXT: nop // Delay Slot 2
; CHECK-NEXT: paddb [sp], #-32; mov r0, r16 // Delay Slot 1
entry:
%cmp = icmp ugt i32 %a, %b
br i1 %cmp, label %if.then, label %if.else
if.then: ; preds = %entry
store i32 %v, i32* %c, align 4
br label %if.end
if.else: ; preds = %entry
call void @foo(i32 %v)
br label %if.end
if.end: ; preds = %if.then, %if.else
ret i32 %v
}
declare void @foo(i32)