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Pull requests: Xilinx/llvm-aie
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[MLIR][Quant] Add DialectInlinerInterface to QuantDialect (#172509)
#755
opened Jan 17, 2026 by
jorickert
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[AIEX] Minimize Stackslots by Decomposition and only keeping defined parts of the Stack
#754
opened Jan 15, 2026 by
F-Stuckmann
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[AIE2P] Disallow s20 to GPR bank mapping in case of anyext users
#751
opened Jan 13, 2026 by
andcarminati
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[NFC] Serialize/Deserialize Register Allocations during Allocation
#750
opened Jan 6, 2026 by
F-Stuckmann
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[AIE] Fix dereferencing an unengaged std::optional<int>.
#744
opened Dec 19, 2025 by
SagarMaheshwari99
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Revert Hotfixes in SubReg Coalescing and Intrinsic Attributes
#735
opened Dec 12, 2025 by
F-Stuckmann
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[AIEX] Refactor Set/GetControlRegister and UPS instruction selection to share common code
#712
opened Nov 17, 2025 by
abhinay-anubola
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[DRAFT] [AIEX] simplify Debug types across AIE architectures
#670
opened Oct 1, 2025 by
F-Stuckmann
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Draft
[AIE2P] Add alternative calling convention for library calls
#664
opened Sep 24, 2025 by
konstantinschwarz
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[DRAFT][AIE2P] Add pseudo to handle VMAC_f_vmac_bf_vmul_bf_core_X_X
#649
opened Sep 11, 2025 by
andcarminati
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[AIE2P][Vectorization] Support for reduction in Peano
#604
opened Aug 7, 2025 by
Sameeranjoshi
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[aie][aie2p] Global Isel : trunc vector when size(src)/size(dst) = 4
#496
opened Jun 20, 2025 by
newling
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[AIE2P] Add SingletonCopyEdges dag mutator in pre-scheduler
#469
opened May 14, 2025 by
khallouh
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[AIE2P] Support all 64-bit-destination G_BUILD_VECTOR in legalizer
#467
opened May 13, 2025 by
khallouh
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[AIE2p] Use multi-slot pseudo for const COPY with unique def
#454
opened May 2, 2025 by
krishnamtibrewala
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[AIE2P] Allow more address chaining and add a profitability check heuristic
#451
opened Apr 28, 2025 by
khallouh
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