Update ADD_NC instr. to use itinerary based on regClass

Author: krishnamtibrewala

llvm/lib/Target/AIE/AIE2GenInstrInfo.td

@@ -14,7 +14,15 @@ let Itinerary = II_ADD in {
   def ADD_add_r_ri : AIE2_add_r_ri_inst_alu<(outs eR:$mRx), (ins eR:$mRx0, simm7:$c7s), "add", "$mRx, $mRx0, $c7s">;
 }
 let Itinerary = II_ADD_NC in {
-  def ADD_NC : AIE2_mv_add_inst_mv<(outs OP_mMvSclDst:$dst), (ins eR:$s0, simm6:$imm), "add.nc", "$dst, $s0, $imm">;
+  let ItineraryRegPairs = [ItinRegClassPair<II_ADD_NC_RS,[OperandRegClass<0, eR>]>,
+                           ItinRegClassPair<II_ADD_NC_P,[OperandRegClass<0, eP>]>, 
+                           ItinRegClassPair<II_ADD_NC_M,[OperandRegClass<0, eM>]>, 
+                           ItinRegClassPair<II_ADD_NC_RS,[OperandRegClass<0, eS>]>, 
+                           ItinRegClassPair<II_ADD_NC_DC,[OperandRegClass<0, eDC>]>,
+                           ItinRegClassPair<II_ADD_NC_DJ,[OperandRegClass<0, eDJ>]>, 
+                           ItinRegClassPair<II_ADD_NC_DN,[OperandRegClass<0, eDN>]>] in {
+    def ADD_NC : AIE2_mv_add_inst_mv<(outs OP_mMvSclDst:$dst), (ins eR:$s0, simm6:$imm), "add.nc", "$dst, $s0, $imm">;
+  }
 }
 // II_ADD_NC_GPR was defined to avoid unnecessary resource dependencies when moving the result into a GPR
 let Itinerary = II_ADD_NC_GPR, isCodeGenOnly = 1 in {

llvm/lib/Target/AIE/AIE2Schedule.td

@@ -150,6 +150,12 @@ def II_ACQ_COND : InstrItinClass;
 def II_ADC : InstrItinClass;
 def II_ADD : InstrItinClass;
 def II_ADD_NC : InstrItinClass;
+def II_ADD_NC_DC : InstrItinClass;
+def II_ADD_NC_DJ : InstrItinClass;
+def II_ADD_NC_DN : InstrItinClass;
+def II_ADD_NC_M : InstrItinClass;
+def II_ADD_NC_P : InstrItinClass;
+def II_ADD_NC_RS : InstrItinClass;
 def II_ADD_NC_GPR : InstrItinClass;
 def II_AND : InstrItinClass;
 def II_ASHL : InstrItinClass;
@@ -436,6 +442,12 @@ InstrItinData<II_ADD, [InstrStage<1,  [R_WX_PORT]>],
 InstrItinData<II_ADD_NC, [PrefixCycle<P_WM_PORT>, PrefixCycle<M_WM_PORT>, PrefixCycle<DJ_WM_PORT>,
                          PrefixCycle<DN_WM_PORT>, PrefixCycle<DC_WM_PORT>, SimpleCycle<RS_WM_PORT>],
                          [1,1,1]>,
+InstrItinData<II_ADD_NC_DC, [SimpleCycle<DC_WM_PORT>], [1,1,1]>,
+InstrItinData<II_ADD_NC_DJ, [SimpleCycle<DJ_WM_PORT>], [1,1,1]>,			  
+InstrItinData<II_ADD_NC_DN, [SimpleCycle<DN_WM_PORT>], [1,1,1]>,
+InstrItinData<II_ADD_NC_M, [SimpleCycle<M_WM_PORT>], [1,1,1]>,
+InstrItinData<II_ADD_NC_P, [SimpleCycle<P_WM_PORT>], [1,1,1]>,
+InstrItinData<II_ADD_NC_RS, [SimpleCycle<RS_WM_PORT>], [1,1,1]>,	                         
 InstrItinData<II_ADD_NC_GPR, [SimpleCycle<RS_WM_PORT>], [1,1,1]>,
 InstrItinData<II_AND, [InstrStage<1,  [R_WX_PORT]>], [1,1,1,1]>,
 InstrItinData<II_ASHL, [InstrStage<1,  [R_WX_PORT]>], [1,1,1,1]>,