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ValentijnvdBeekValentijnvdBeek
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[AIE2] Support for 64-bit G_BUILD_VECTOR and G_UNMERGE_VALUES
1 parent 118f973 commit 226d716

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4 files changed

+253
-34
lines changed

4 files changed

+253
-34
lines changed

Diff for: ‎llvm/lib/Target/AIE/AIELegalizerInfo.cpp

+34-30
Original file line numberDiff line numberDiff line change
@@ -89,7 +89,7 @@ static LegalityPredicate isValidVectorAIE2(const unsigned TypeIdx) {
8989
return [=](const LegalityQuery &Query) {
9090
const LLT DstTy = Query.Types[TypeIdx];
9191
const unsigned DstSize = DstTy.getSizeInBits();
92-
return DstTy.isVector() && (DstSize == 32 || DstSize > 64);
92+
return DstTy.isVector() && (DstSize >= 32);
9393
};
9494
}
9595

@@ -551,44 +551,46 @@ bool AIELegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
551551
llvm_unreachable("Un-expected custom legalization");
552552
}
553553

554-
bool AIELegalizerInfo::pack32BitVector(LegalizerHelper &Helper,
555-
MachineInstr &MI,
556-
Register SourceReg) const {
554+
bool AIELegalizerInfo::packBitVector(LegalizerHelper &Helper,
555+
MachineInstr &MI) const {
557556
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
558557
MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
559558

560-
const LLT SourceRegTy = MRI.getType(SourceReg);
561559
const Register DstReg = MI.getOperand(0).getReg();
562-
assert(SourceRegTy.getSizeInBits() == 32 &&
563-
"cannot pack vectors larger or smaller than 32-bit");
560+
const LLT DstRegTy = MRI.getType(DstReg);
561+
assert(DstRegTy.getSizeInBits() == 32 ||
562+
DstRegTy.getSizeInBits() == 64 &&
563+
"can only pack 32- and 64-bit vectors");
564564

565-
const LLT S32 = LLT::scalar(32);
565+
const LLT STy = LLT::scalar(MRI.getType(DstReg).getSizeInBits());
566566
unsigned Offset = 0;
567-
Register DstCastReg = MRI.createGenericVirtualRegister(S32);
567+
Register DstCastReg = MRI.createGenericVirtualRegister(STy);
568568

569569
// Skip the destination operand since that is where we are writing to.
570570
MachineOperand *Operand = MI.operands_begin() + 1,
571571
*OperandEnd = MI.operands_end();
572572
MIRBuilder.buildConstant(DstCastReg, 0);
573573

574-
const LLT RegTy = MRI.getType(DstReg);
574+
const LLT RegTy = MRI.getType(Operand->getReg());
575575
while (Operand != OperandEnd) {
576576
Register DestinationOperand = Operand->getReg();
577577

578-
if (RegTy.getScalarSizeInBits() != 32) {
579-
const Register TmpReg32 = MRI.createGenericVirtualRegister(S32);
580-
MIRBuilder.buildInstr(AIE2::G_ZEXT, {TmpReg32}, {DestinationOperand});
581-
DestinationOperand = TmpReg32;
578+
const LLT S32 = LLT::scalar(32);
579+
if (RegTy != STy) {
580+
const Register TmpReg = MRI.createGenericVirtualRegister(STy);
581+
MIRBuilder.buildInstr(AIE2::G_ZEXT, {TmpReg}, {DestinationOperand});
582+
DestinationOperand = TmpReg;
582583
}
583584

584585
// Avoid a useless shift for the first element, since it doesn't get
585586
// optimized out in O0.
586-
const Register AccumulatorReg = MRI.createGenericVirtualRegister(S32);
587+
const Register AccumulatorReg = MRI.createGenericVirtualRegister(STy);
588+
587589
if (Offset != 0) {
588590
const MachineInstrBuilder ShiftConstant =
589591
MIRBuilder.buildConstant(S32, Offset);
590592
const MachineInstrBuilder Masked =
591-
MIRBuilder.buildShl(S32, DestinationOperand, ShiftConstant);
593+
MIRBuilder.buildShl(STy, DestinationOperand, ShiftConstant);
592594
MIRBuilder.buildOr(AccumulatorReg, DstCastReg, Masked);
593595
} else {
594596
MIRBuilder.buildOr(AccumulatorReg, DstCastReg, DestinationOperand);
@@ -604,19 +606,20 @@ bool AIELegalizerInfo::pack32BitVector(LegalizerHelper &Helper,
604606
return true;
605607
}
606608

607-
bool AIELegalizerInfo::unpack32BitVector(LegalizerHelper &Helper,
608-
MachineInstr &MI,
609-
Register SourceReg) const {
609+
bool AIELegalizerInfo::unpackBitVector(LegalizerHelper &Helper,
610+
MachineInstr &MI) const {
610611
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
611612
MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
612613

614+
const Register SourceReg = MI.getOperand(MI.getNumOperands() - 1).getReg();
613615
const LLT SourceRegTy = MRI.getType(SourceReg);
614-
assert(SourceRegTy.getSizeInBits() == 32 &&
615-
"cannot unpack vectors larger or smaller than 32-bit");
616+
assert(SourceRegTy.getSizeInBits() == 32 ||
617+
SourceRegTy.getSizeInBits() == 64 &&
618+
"can only unpack 32- and 64-bit vectors");
616619

617-
const LLT S32 = LLT::scalar(32);
618620
unsigned Offset = 0;
619-
Register DstCastReg = MRI.createGenericVirtualRegister(S32);
621+
const LLT STy = LLT::scalar(SourceRegTy.getSizeInBits());
622+
Register DstCastReg = MRI.createGenericVirtualRegister(STy);
620623

621624
MachineOperand *Operand = MI.operands_begin(),
622625
*OperandEnd = MI.operands_end() - 1;
@@ -627,10 +630,11 @@ bool AIELegalizerInfo::unpack32BitVector(LegalizerHelper &Helper,
627630
// Avoid a useless shift for the first element, since it doesn't get
628631
// optimized out in O0.
629632
if (Offset != 0) {
633+
const LLT S32 = LLT::scalar(32);
630634
const MachineInstrBuilder ShiftConstant =
631635
MIRBuilder.buildConstant(S32, Offset);
632636
const MachineInstrBuilder Masked =
633-
MIRBuilder.buildLShr(S32, DstCastReg, ShiftConstant);
637+
MIRBuilder.buildLShr(STy, DstCastReg, ShiftConstant);
634638
MIRBuilder.buildTrunc(DestinationOperand, Masked);
635639

636640
} else {
@@ -658,13 +662,13 @@ bool AIELegalizerInfo::legalizeG_BUILD_VECTOR(LegalizerHelper &Helper,
658662
const unsigned EltSize = DstVecEltTy.getScalarSizeInBits();
659663
assert((EltSize == 8 || EltSize == 16 || EltSize == 32) &&
660664
"non-existent integer size");
661-
assert(DstVecSize == 32 || (DstVecSize > 64 && DstVecSize <= 1024 &&
662-
"non-native vectors are not supported"));
665+
assert(DstVecSize >= 32 && DstVecSize <= 1024 &&
666+
"non-native vectors are not supported");
663667
assert(DstVecSize < 1024 && "vadd takes a 512-bit argument");
664668

665669
// If our vector is 32-bit we can store it as packed integer vector
666-
if (DstVecSize == 32)
667-
return pack32BitVector(Helper, MI, DstReg);
670+
if (DstVecSize == 32 || DstVecSize == 64)
671+
return packBitVector(Helper, MI);
668672

669673
// We are using an undef since we are building over multiple instructions
670674
const TypeSize VecEltTySize = DstVecEltTy.getSizeInBits();
@@ -724,8 +728,8 @@ bool AIELegalizerInfo::legalizeG_UNMERGE_VALUES(LegalizerHelper &Helper,
724728
LastTy.getSizeInBits() &&
725729
"This operation is only supported for vectors");
726730

727-
if (LastTy.getSizeInBits() == 32)
728-
return unpack32BitVector(Helper, MI, LastReg);
731+
if (LastTy.getSizeInBits() == 32 || LastTy.getSizeInBits() == 64)
732+
return unpackBitVector(Helper, MI);
729733

730734
// Pad vectors of 128-bit vectors to 256-bit
731735
Register TargetReg = LastReg;

Diff for: ‎llvm/lib/Target/AIE/AIELegalizerInfo.h

+2-4
Original file line numberDiff line numberDiff line change
@@ -51,10 +51,8 @@ class AIELegalizerInfo : public LegalizerInfo {
5151
bool legalizeG_FADDSUB(LegalizerHelper &Helper, MachineInstr &MI) const;
5252

5353
// Helper functions for legalization
54-
bool pack32BitVector(LegalizerHelper &Helper, MachineInstr &MI,
55-
Register SourceReg) const;
56-
bool unpack32BitVector(LegalizerHelper &Helper, MachineInstr &MI,
57-
Register SourceReg) const;
54+
bool packBitVector(LegalizerHelper &Helper, MachineInstr &MI) const;
55+
bool unpackBitVector(LegalizerHelper &Helper, MachineInstr &MI) const;
5856
};
5957
} // end namespace llvm
6058
#endif

Diff for: ‎llvm/test/CodeGen/AIE/aie2/GlobalISel/legalize-build-vector.mir

+108
Original file line numberDiff line numberDiff line change
@@ -661,3 +661,111 @@ body: |
661661
%5:_(s8) = G_TRUNC %1(s32)
662662
%6:_(<4 x s8>) = G_BUILD_VECTOR %2(s8), %3(s8), %4(s8), %5(s8)
663663
PseudoRET implicit $lr, implicit %6
664+
...
665+
666+
---
667+
name: test_build_vector_64_16
668+
body: |
669+
bb.1.entry:
670+
; CHECK-LABEL: name: test_build_vector_64_16
671+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
672+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
673+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
674+
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
675+
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
676+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
677+
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
678+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[C]], [[C5]]
679+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
680+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C4]], [[AND]]
681+
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C4]], [[AND1]]
682+
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[C1]], [[C5]]
683+
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
684+
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
685+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C6]](s32)
686+
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
687+
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C6]](s32)
688+
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
689+
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL]]
690+
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[OR2]]
691+
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[C2]], [[C5]]
692+
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[C4]]
693+
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[AND4]]
694+
; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[C3]], [[C5]]
695+
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C6]](s32)
696+
; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[C4]]
697+
; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL2]]
698+
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR7]](s32), [[OR8]](s32)
699+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s16>) = G_BITCAST [[MV]](s64)
700+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[BITCAST]](<4 x s16>)
701+
%0:_(s16) = G_CONSTANT i16 1
702+
%1:_(s16) = G_CONSTANT i16 2
703+
%2:_(s16) = G_CONSTANT i16 3
704+
%3:_(s16) = G_CONSTANT i16 4
705+
%4:_(<4 x s16>) = G_BUILD_VECTOR %0(s16), %1(s16), %2(s16), %3(s16)
706+
PseudoRET implicit $lr, implicit %4
707+
...
708+
709+
---
710+
name: test_build_vector_64_8
711+
body: |
712+
bb.1.entry:
713+
; CHECK-LABEL: name: test_build_vector_64_8
714+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
715+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
716+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
717+
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
718+
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
719+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
720+
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
721+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[C]], [[C5]]
722+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
723+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C4]], [[AND]]
724+
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C4]], [[AND1]]
725+
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[C1]], [[C5]]
726+
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
727+
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
728+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C6]](s32)
729+
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
730+
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
731+
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C7]](s32)
732+
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
733+
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL]]
734+
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[OR2]]
735+
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[C2]], [[C5]]
736+
; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
737+
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
738+
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C8]](s32)
739+
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C8]](s32)
740+
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C8]](s32)
741+
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[LSHR1]]
742+
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL2]]
743+
; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]]
744+
; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[C3]], [[C5]]
745+
; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
746+
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C7]](s32)
747+
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C7]](s32)
748+
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C6]](s32)
749+
; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[LSHR2]]
750+
; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL4]]
751+
; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[OR8]]
752+
; CHECK-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[C4]]
753+
; CHECK-NEXT: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[AND6]]
754+
; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C6]](s32)
755+
; CHECK-NEXT: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[C4]]
756+
; CHECK-NEXT: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL6]]
757+
; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C8]](s32)
758+
; CHECK-NEXT: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[C4]]
759+
; CHECK-NEXT: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL7]]
760+
; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C7]](s32)
761+
; CHECK-NEXT: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[C4]]
762+
; CHECK-NEXT: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL8]]
763+
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR17]](s32), [[OR18]](s32)
764+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[MV]](s64)
765+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[BITCAST]](<8 x s8>)
766+
%0:_(s8) = G_CONSTANT i8 1
767+
%1:_(s8) = G_CONSTANT i8 2
768+
%2:_(s8) = G_CONSTANT i8 3
769+
%3:_(s8) = G_CONSTANT i8 4
770+
%4:_(<8 x s8>) = G_BUILD_VECTOR %0(s8), %1(s8), %2(s8), %3(s8), %3(s8), %2(s8), %1(s8), %0(s8)
771+
PseudoRET implicit $lr, implicit %4

Diff for: ‎llvm/test/CodeGen/AIE/aie2/GlobalISel/legalize-unmerge-values.mir

+109
Original file line numberDiff line numberDiff line change
@@ -525,3 +525,112 @@ body: |
525525
%1(s32), %2(s32), %3(s32), %4(s32) = G_UNMERGE_VALUES %5(<4 x s32>)
526526
PseudoRET implicit $lr, implicit %1, implicit %2, implicit %3, implicit %4
527527
...
528+
---
529+
name: test_unmerge_v4s16
530+
registers:
531+
- { id: 0, class: _, preferred-register: '' }
532+
- { id: 1, class: _, preferred-register: '' }
533+
- { id: 2, class: _, preferred-register: '' }
534+
- { id: 3, class: _, preferred-register: '' }
535+
- { id: 4, class: _, preferred-register: '' }
536+
- { id: 5, class: _, preferred-register: '' }
537+
- { id: 6, class: _, preferred-register: '' }
538+
- { id: 7, class: _, preferred-register: '' }
539+
- { id: 8, class: _, preferred-register: '' }
540+
legalized: false
541+
body: |
542+
bb.0.entry:
543+
liveins: $l0
544+
; CHECK-LABEL: name: test_unmerge_v4s16
545+
; CHECK: liveins: $l0
546+
; CHECK-NEXT: {{ $}}
547+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $l0
548+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[COPY]](<4 x s16>)
549+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
550+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s64)
551+
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
552+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
553+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[SEXT_INREG]](s32)
554+
%0:_(<4 x s16>) = COPY $l0
555+
%1(s16), %2(s16), %3(s16), %4(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
556+
%5(s32) = G_SEXT %4(s16)
557+
PseudoRET implicit $lr, implicit %5
558+
...
559+
---
560+
name: test_unmerge_v8s8
561+
registers:
562+
- { id: 0, class: _, preferred-register: '' }
563+
- { id: 1, class: _, preferred-register: '' }
564+
- { id: 2, class: _, preferred-register: '' }
565+
- { id: 3, class: _, preferred-register: '' }
566+
- { id: 4, class: _, preferred-register: '' }
567+
- { id: 5, class: _, preferred-register: '' }
568+
- { id: 6, class: _, preferred-register: '' }
569+
- { id: 7, class: _, preferred-register: '' }
570+
- { id: 8, class: _, preferred-register: '' }
571+
- { id: 9, class: _, preferred-register: '' }
572+
573+
legalized: false
574+
body: |
575+
bb.0.entry:
576+
liveins: $l0
577+
; CHECK-LABEL: name: test_unmerge_v8s8
578+
; CHECK: liveins: $l0
579+
; CHECK-NEXT: {{ $}}
580+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $l0
581+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[COPY]](<8 x s8>)
582+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
583+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
584+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s64)
585+
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
586+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
587+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
588+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[OR]], 8
589+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[SEXT_INREG]](s32)
590+
%0:_(<8 x s8>) = COPY $l0
591+
%1(s8), %2(s8), %3(s8), %4(s8), %5(s8), %6(s8), %7(s8), %8(s8) = G_UNMERGE_VALUES %0(<8 x s8>)
592+
%9(s32) = G_SEXT %4(s8)
593+
PseudoRET implicit $lr, implicit %9
594+
...
595+
---
596+
name: test_unmerge_64bit_order
597+
registers:
598+
- { id: 0, class: _, preferred-register: '' }
599+
- { id: 1, class: _, preferred-register: '' }
600+
- { id: 2, class: _, preferred-register: '' }
601+
- { id: 3, class: _, preferred-register: '' }
602+
- { id: 4, class: _, preferred-register: '' }
603+
- { id: 5, class: _, preferred-register: '' }
604+
- { id: 6, class: _, preferred-register: '' }
605+
- { id: 7, class: _, preferred-register: '' }
606+
- { id: 8, class: _, preferred-register: '' }
607+
legalized: false
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body: |
609+
bb.0.entry:
610+
liveins: $l0
611+
; CHECK-LABEL: name: test_unmerge_64bit_order
612+
; CHECK: liveins: $l0
613+
; CHECK-NEXT: {{ $}}
614+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $l0
615+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[COPY]](<4 x s16>)
616+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
617+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s64)
618+
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
619+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
620+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
621+
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s64)
622+
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s64)
623+
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
624+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[BITCAST]](s64)
625+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 16
626+
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[OR]], 16
627+
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV3]], 16
628+
; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
629+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[SEXT_INREG]](s32), implicit [[SEXT_INREG1]](s32), implicit [[SEXT_INREG2]](s32), implicit [[SEXT_INREG3]](s32)
630+
%0:_(<4 x s16>) = COPY $l0
631+
%1(s16), %2(s16), %3(s16), %4(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
632+
%5(s32) = G_SEXT %1(s16)
633+
%6(s32) = G_SEXT %2(s16)
634+
%7(s32) = G_SEXT %3(s16)
635+
%8(s32) = G_SEXT %4(s16)
636+
PseudoRET implicit $lr, implicit %5, implicit %6, implicit %7, implicit %8

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