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| 1 | +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| 2 | +# |
| 3 | +# This file is licensed under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +# See https://llvm.org/LICENSE.txt for license information. |
| 5 | +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +# |
| 7 | +# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates |
| 8 | + |
| 9 | +# RUN: llc -mtriple aie2 -run-pass=legalizer %s -verify-machineinstrs -o - \ |
| 10 | +# RUN: | FileCheck %s |
| 11 | + |
| 12 | +# This test checks legalization of the saturated operations for ADD and SUB |
| 13 | +# in signed and unsigned variants |
| 14 | + |
| 15 | +--- |
| 16 | +name: uaddsat |
| 17 | +body: | |
| 18 | + ; CHECK-LABEL: name: uaddsat |
| 19 | + ; CHECK: bb.0: |
| 20 | + ; CHECK-NEXT: successors: %bb.1(0x80000000) |
| 21 | + ; CHECK-NEXT: liveins: $r0, $r1 |
| 22 | + ; CHECK-NEXT: {{ $}} |
| 23 | + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r0 |
| 24 | + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r1 |
| 25 | + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] |
| 26 | + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]] |
| 27 | + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| 28 | + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C]], [[ADD]] |
| 29 | + ; CHECK-NEXT: $r0 = COPY [[SELECT]](s32) |
| 30 | + ; CHECK-NEXT: {{ $}} |
| 31 | + ; CHECK-NEXT: bb.1: |
| 32 | + ; CHECK-NEXT: PseudoRET implicit $lr, implicit $r0 |
| 33 | + bb.1: |
| 34 | + liveins: $r0, $r1 |
| 35 | + %3:_(s32) = COPY $r0 |
| 36 | + %4:_(s32) = COPY $r1 |
| 37 | + %5:_(s32) = G_UADDSAT %3, %4 |
| 38 | + $r0 = COPY %5 |
| 39 | + bb.2: |
| 40 | + PseudoRET implicit $lr, implicit $r0 |
| 41 | +... |
| 42 | + |
| 43 | +--- |
| 44 | +name: usubsat |
| 45 | +body: | |
| 46 | + ; CHECK-LABEL: name: usubsat |
| 47 | + ; CHECK: bb.0: |
| 48 | + ; CHECK-NEXT: successors: %bb.1(0x80000000) |
| 49 | + ; CHECK-NEXT: liveins: $r0, $r1 |
| 50 | + ; CHECK-NEXT: {{ $}} |
| 51 | + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r0 |
| 52 | + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r1 |
| 53 | + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] |
| 54 | + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]] |
| 55 | + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| 56 | + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C]], [[SUB]] |
| 57 | + ; CHECK-NEXT: $r0 = COPY [[SELECT]](s32) |
| 58 | + ; CHECK-NEXT: {{ $}} |
| 59 | + ; CHECK-NEXT: bb.1: |
| 60 | + ; CHECK-NEXT: PseudoRET implicit $lr, implicit $r0 |
| 61 | + bb.1: |
| 62 | + liveins: $r0, $r1 |
| 63 | + %3:_(s32) = COPY $r0 |
| 64 | + %4:_(s32) = COPY $r1 |
| 65 | + %5:_(s32) = G_USUBSAT %3, %4 |
| 66 | + $r0 = COPY %5 |
| 67 | + bb.2: |
| 68 | + PseudoRET implicit $lr, implicit $r0 |
| 69 | +... |
| 70 | + |
| 71 | +--- |
| 72 | +name: saddsat |
| 73 | +body: | |
| 74 | + ; CHECK-LABEL: name: saddsat |
| 75 | + ; CHECK: bb.0: |
| 76 | + ; CHECK-NEXT: successors: %bb.1(0x80000000) |
| 77 | + ; CHECK-NEXT: liveins: $r0, $r1 |
| 78 | + ; CHECK-NEXT: {{ $}} |
| 79 | + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r0 |
| 80 | + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r1 |
| 81 | + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] |
| 82 | + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| 83 | + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ADD]](s32), [[COPY]] |
| 84 | + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[C]] |
| 85 | + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP1]], [[ICMP]] |
| 86 | + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 |
| 87 | + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C1]](s32) |
| 88 | + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 |
| 89 | + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]] |
| 90 | + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[XOR]](s32), [[ADD1]], [[ADD]] |
| 91 | + ; CHECK-NEXT: $r0 = COPY [[SELECT]](s32) |
| 92 | + ; CHECK-NEXT: {{ $}} |
| 93 | + ; CHECK-NEXT: bb.1: |
| 94 | + ; CHECK-NEXT: PseudoRET implicit $lr, implicit $r0 |
| 95 | + bb.1: |
| 96 | + liveins: $r0, $r1 |
| 97 | + %3:_(s32) = COPY $r0 |
| 98 | + %4:_(s32) = COPY $r1 |
| 99 | + %5:_(s32) = G_SADDSAT %3, %4 |
| 100 | + $r0 = COPY %5 |
| 101 | + bb.2: |
| 102 | + PseudoRET implicit $lr, implicit $r0 |
| 103 | +... |
| 104 | + |
| 105 | +--- |
| 106 | +name: ssubsat |
| 107 | +body: | |
| 108 | + ; CHECK-LABEL: name: ssubsat |
| 109 | + ; CHECK: bb.0: |
| 110 | + ; CHECK-NEXT: successors: %bb.1(0x80000000) |
| 111 | + ; CHECK-NEXT: liveins: $r0, $r1 |
| 112 | + ; CHECK-NEXT: {{ $}} |
| 113 | + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r0 |
| 114 | + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r1 |
| 115 | + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] |
| 116 | + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| 117 | + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB]](s32), [[COPY]] |
| 118 | + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[C]] |
| 119 | + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP1]], [[ICMP]] |
| 120 | + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 |
| 121 | + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB]], [[C1]](s32) |
| 122 | + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 |
| 123 | + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]] |
| 124 | + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[XOR]](s32), [[ADD]], [[SUB]] |
| 125 | + ; CHECK-NEXT: $r0 = COPY [[SELECT]](s32) |
| 126 | + ; CHECK-NEXT: {{ $}} |
| 127 | + ; CHECK-NEXT: bb.1: |
| 128 | + ; CHECK-NEXT: PseudoRET implicit $lr, implicit $r0 |
| 129 | + bb.1: |
| 130 | + liveins: $r0, $r1 |
| 131 | + %3:_(s32) = COPY $r0 |
| 132 | + %4:_(s32) = COPY $r1 |
| 133 | + %5:_(s32) = G_SSUBSAT %3, %4 |
| 134 | + $r0 = COPY %5 |
| 135 | + bb.2: |
| 136 | + PseudoRET implicit $lr, implicit $r0 |
| 137 | +... |
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