[AIE2P][AIE2] Split symmetric G_BUILD_VECTOR into two G_BUILD_VECTORs

Author: abhinay-anubola

llvm/lib/Target/AIE/AIECombine.td

@@ -9,6 +9,29 @@
 //===----------------------------------------------------------------------===//
 include "llvm/Target/GlobalISel/Combine.td"
 
+def aie_all_combines : GICombineGroup<[trivial_combines, vector_ops_combines,
+    insert_vec_elt_combines, extract_vec_elt_combines, combines_for_extload,
+    combine_extracted_vector_load,
+    undef_combines, identity_combines, phi_combines,
+    simplify_add_to_sub, hoist_logic_op_with_same_opcode_hands, shifts_too_big,
+    reassocs, ptr_add_immed_chain,
+    shl_ashr_to_sext_inreg, sext_inreg_of_load,
+    width_reduction_combines, select_combines,
+    known_bits_simplifications, ext_ext_fold,
+    not_cmp_fold, opt_brcond_by_inverting_cond,
+    unmerge_merge, unmerge_cst, unmerge_dead_to_trunc,
+    unmerge_zext_to_zext, merge_unmerge, trunc_ext_fold, trunc_shift,
+    const_combines, xor_of_and_with_same_reg, ptr_add_with_zero,
+    shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine,
+    div_rem_to_divrem, funnel_shift_combines, commute_shift,
+    form_bitfield_extract, constant_fold_binops, constant_fold_fma,
+    constant_fold_cast_op, fabs_fneg_fold,
+    intdiv_combines, mulh_combines, redundant_neg_operands,
+    and_or_disjoint_mask, fma_combines, fold_binop_into_select,
+    sub_add_reg, select_to_minmax, redundant_binop_in_equality,
+    fsub_to_fneg, commute_constant_to_rhs, match_ands, match_ors,
+    double_icmp_zero_and_or_combine, match_addos, combine_shuffle_concat]>;
+
 // AIE-specific offset folding for G_GLOBAL_VALUE.
 def combine_globalval_offset_matchdata : GIDefMatchData<"uint64_t">;
 def combine_globalval_offset : GICombineRule<
@@ -34,6 +57,13 @@ def combine_extract_vector_elt_and_zsa_ext : GICombineRule<
   (apply [{ applyExtractVecEltAndExt(*${root}, MRI, B, ${matchinfo}); }])
 >;
 
+def combine_symmetric_build_vector : GICombineRule<
+  (defs root:$root, build_fn_matchinfo:$matchinfo),
+  (match (wip_match_opcode G_BUILD_VECTOR): $root,
+  [{ return matchSymmetricBuildVector(*${root}, MRI, Observer, ${matchinfo}); }]),
+  (apply [{ Helper.applyBuildFnNoErase(*${root}, ${matchinfo}); }])
+>;
+
 def combine_splat_vector_matchdata: GIDefMatchData<"std::pair<Register, Register>">;
 def combine_splat_vector : GICombineRule<
   (defs root:$root, combine_splat_vector_matchdata:$matchinfo),
@@ -122,19 +152,20 @@ def combine_vector_shuffle_bcst_to_copy : GICombineRule<
 
 def AIE2PreLegalizerCombiner
     : GICombiner<"AIE2PreLegalizerCombinerImpl", [ combine_unpad_vector, combine_pad_vector,
-                                                                 all_combines, combine_S20NarrowingOpt,
+                                                                 aie_all_combines, combine_S20NarrowingOpt,
                                                                  combine_globalval_offset,
                                                                  combine_extract_vector_elt_and_zsa_ext,
                                                                  combine_splat_vector, combine_concat_to_pad_vector, 
-                                                                 combine_single_diff_build_vector]> {
+                                                                 combine_single_diff_build_vector,
+                                                                 combine_symmetric_build_vector]> {
   let CombineAllMethodName = "tryCombineAllImpl";
 }
 
 def AIE2PPreLegalizerCombiner
     : GICombiner<"AIE2PPreLegalizerCombinerImpl", [ combine_unpad_vector, combine_pad_vector,
                                                                  combine_vector_shuffle_to_copy,
                                                                  combine_vector_shuffle_extract_subvec,
-                                                                 all_combines, combine_S20NarrowingOpt,
+                                                                 aie_all_combines, combine_S20NarrowingOpt,
                                                                  combine_globalval_offset,
                                                                  combine_extract_vector_elt_and_zsa_ext,
                                                                  combine_splat_vector, 
@@ -145,16 +176,17 @@ def AIE2PPreLegalizerCombiner
                                                                  combine_vector_shuffle_broadcast,
                                                                  combine_single_diff_build_vector,
                                                                  combine_vector_shuffle_to_extract_insert_elt,
-                                                                 combine_vector_shuffle_concat_extracted_subvectors]> {
+                                                                 combine_vector_shuffle_concat_extracted_subvectors,
+                                                                 combine_symmetric_build_vector]> {
   let CombineAllMethodName = "tryCombineAllImpl";
 }
 
 def AIE2PostLegalizerGenericCombiner
-    : GICombiner<"AIE2PostLegalizerGenericCombinerImpl", [ all_combines ]> {
+    : GICombiner<"AIE2PostLegalizerGenericCombinerImpl", [ aie_all_combines ]> {
 }
 
 def AIE2PPostLegalizerGenericCombiner
-    : GICombiner<"AIE2PPostLegalizerGenericCombinerImpl", [ all_combines ]> {
+    : GICombiner<"AIE2PPostLegalizerGenericCombinerImpl", [ aie_all_combines ]> {
 }
 
 def combine_extract_concat_matchdata: GIDefMatchData<"Register">;

llvm/lib/Target/AIE/AIECombinerHelper.cpp

@@ -16,6 +16,7 @@
 #include "llvm/ADT/SetVector.h"
 #include "llvm/Analysis/VectorUtils.h"
 #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineInstr.h"
@@ -1385,6 +1386,72 @@ bool llvm::applySingleDiffLaneBuildVector(
   return true;
 }
 
+// Match something like:
+// %0:_(<32 x s16>) = G_BUILD_VECTOR %1:_(s16), ... x16, %2:_(s16), ... x16
+//
+// To turn it into
+// %3:_(<16 x s16>) = G_BUILD_VECTOR %1:_(s16), ... x16
+// %4:_(<16 x s16>) = G_BUILD_VECTOR %2:_(s16), ... x16
+// %0:_(<32 x s16>) = G_CONCAT_VECTORS %3:_(<16 x s16>), %4:_(<16 x s16>)
+// These sub-G_BUILD_VECTOR instructions may later be combined into broadcast
+// instructions by combine_splat_vector.
+bool llvm::matchSymmetricBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI,
+                                     GISelChangeObserver &Observer,
+                                     BuildFnTy &MatchInfo) {
+
+  assert(MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR &&
+         "Expected a G_BUILD_VECTOR");
+  const Register DstVecReg = MI.getOperand(0).getReg();
+  const LLT DstVecTy = MRI.getType(DstVecReg);
+  const unsigned DstVecSize = DstVecTy.getSizeInBits();
+
+  switch (DstVecSize) {
+  case 256:
+  case 512:
+  case 1024:
+  case 2048:
+    break;
+  default:
+    // unimplemented
+    return false;
+  }
+
+  auto getSrcOperand = [&](unsigned I) { return MI.getOperand(I + 1); };
+
+  const unsigned NumElts = MI.getNumOperands() - 1;
+  const unsigned HalfNumElts = NumElts / 2;
+  const MachineOperand FirstOp = getSrcOperand(0);
+  const MachineOperand SecondOp = getSrcOperand(HalfNumElts);
+
+  // Ensures that each operand in the first half matches FirstOp, and each
+  // operand in the second half matches SecondOp.
+  for (unsigned i = 0; i < HalfNumElts; i++) {
+    if (!getSrcOperand(i).isIdenticalTo(FirstOp)) {
+      return false;
+    }
+    if (!getSrcOperand(HalfNumElts + i).isIdenticalTo(SecondOp)) {
+      return false;
+    }
+  }
+
+  // If both halves are the same register, it's effectively a splat, and the
+  // splat vector combine already handles that case.
+  if (FirstOp.isIdenticalTo(SecondOp))
+    return false;
+
+  MatchInfo = [&MI, &Observer, &MRI, DstVecTy](MachineIRBuilder &B) {
+    B.setInstrAndDebugLoc(MI);
+    LegalizerHelper Helper(B.getMF(), Observer, B);
+    // Splits the G_BUILD_VECTOR into two half-sized G_BUILD_VECTOR operations
+    // and then emits a G_CONCAT_VECTORS to combine them into final vector.
+    Helper.fewerElementsVector(
+        MI, 0,
+        DstVecTy.changeElementCount(
+            DstVecTy.getElementCount().divideCoefficientBy(2)));
+  };
+  return true;
+}
+
 // Match something like:
 // %0(<4 x s32>), dead %1(<4 x s32>), dead %2(<4 x s32>), dead %3(<4 x s32>)
 //   = G_UNMERGE_VALUES %10(<16 x s32>)

llvm/lib/Target/AIE/AIECombinerHelper.h

@@ -206,6 +206,10 @@ bool applySingleDiffLaneBuildVector(
     MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
     AIESingleDiffLaneBuildVectorMatchData &MatchInfo);
 
+bool matchSymmetricBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI,
+                               GISelChangeObserver &Observer,
+                               BuildFnTy &MatchInfo);
+
 bool matchUnpadVector(MachineInstr &MI, MachineRegisterInfo &MRI,
                       const AIEBaseInstrInfo &TII);
 void applyUnpadVector(MachineInstr &MI, MachineRegisterInfo &MRI,