[AIE] ReservedRegsLICM: fix exit-sink to scan the exiting block, not the latch

processForExitSink was scanning L.getLoopLatch() for sink candidates.
When the latch and the exiting block differ, instructions in the latch
are not on the exit path: sinking them to the exit block inserts a def
that was never executed on that path, corrupting the register's value
at the exit.

Fix this by scanning L.getExitingBlock() instead. The guard that checks
whether a register is live at the entry of the scanned block is also
updated to use the exiting block (renamed LatchEntryLive ->
ExitingBlockEntryLive).

Add a test case (latch_vs_exiting_no_sink) that reproduces the bug:
a loop where the latch (bb.3) defines $srssign0 = MOVX 0 but the
exiting block (bb.2) exits directly to bb.4 without going through bb.3.
The MOVX must remain in bb.3.

Author: andcarminati

llvm/lib/Target/AIE/ReservedRegsLICM.cpp

@@ -341,36 +341,44 @@ static void moveInstruction(const CandidateInfo &Cand,
 
 void ReservedRegsLICM::processForExitSink(MachineLoop &L,
                                           const BitVector &ReservedLiveins) {
-  // Pre-compute what's live at the entry of the latch block by walking it
+  // Sink candidates must come from the exiting block (the block that has the
+  // edge to the exit block), not the latch. When the latch and the exiting
+  // block differ, instructions in the latch are not on the exit path: sinking
+  // them to the exit block would insert a def that was never executed on that
+  // path, corrupting the register's exit value.
+  MachineBasicBlock *ExitingBlock = L.getExitingBlock();
+  assert(ExitingBlock);
+
+  // Pre-compute what's live at the entry of the exiting block by walking it
   // fully backward. For multi-block loops with conditional paths, a candidate
   // register may be defined in some branches but not others, making it live at
-  // the latch entry on those paths. If the register is live at the latch entry
-  // (i.e., used before its first def in the latch), sinking its last def to
-  // the exit block would expose the wrong value on those paths.
-  assert(L.getLoopLatch());
-  LivePhysRegs LatchEntryLive(*TRI);
-  for (const MachineInstr &MI : reverse(*L.getLoopLatch()))
-    LatchEntryLive.stepBackward(MI);
+  // the exiting block entry on those paths. If the register is live at the
+  // exiting block entry (i.e., used before its first def in the exiting block,
+  // possibly carrying a value from a conditional path that skips the def),
+  // sinking its last def to the exit block would expose the wrong value.
+  LivePhysRegs ExitingBlockEntryLive(*TRI);
+  for (const MachineInstr &MI : reverse(*ExitingBlock))
+    ExitingBlockEntryLive.stepBackward(MI);
 
   RegDefMap PhysRegChanged(*TRI);
   LivePhysRegs LiveRegs(*TRI);
   Candidates SinkCandidates;
 
-  // Walk the latch block, track defs for each register, and
+  // Walk the exiting block, track defs for each register, and
   // collect potential LICM candidates.
-  for (MachineInstr &MI : reverse(*L.getLoopLatch())) {
+  for (MachineInstr &MI : reverse(*ExitingBlock)) {
     CandidateInfo *CandInfo = SinkCandidates.getInfo(MI);
 
     // First time we meet a reserved reg definition while iterating upwards.
     // If that def is not a loop livein, it isn't used in this block after the
-    // def, and it isn't live at the latch entry (which would indicate it is
-    // used before its def in the latch, possibly carrying a value from a
-    // conditional path that skips the def), then one can move the instruction
-    // to the exit BB of the loop.
+    // def, and it isn't live at the exiting block entry (which would indicate
+    // it is used before its def in the exiting block, possibly carrying a
+    // value from a conditional path that skips the def), then one can move
+    // the instruction to the exit BB of the loop.
     if (CandInfo && !PhysRegChanged.hasChanged(CandInfo->DefinedReg) &&
         !ReservedLiveins.test(CandInfo->DefinedReg) &&
         !LiveRegs.contains(CandInfo->DefinedReg) &&
-        !LatchEntryLive.contains(CandInfo->DefinedReg)) {
+        !ExitingBlockEntryLive.contains(CandInfo->DefinedReg)) {
       assert(!CandInfo->HoistCandidate);
       CandInfo->HoistCandidate = &MI;
     }

llvm/test/CodeGen/AIE/aie2ps/reserved-reg-licm.mir

@@ -436,6 +436,77 @@ body:             |
     PseudoJ_jump_imm %bb.1
 ...
 
+# The latch (bb.3) defines $srssign0 = MOVX 0 but is NOT the exiting block.
+# The exiting block (bb.2) exits to bb.4 without going through bb.3, so the
+# MOVX is not on the exit path. processForExitSink must scan the exiting block
+# (bb.2), not the latch (bb.3), to avoid sinking the MOVX to bb.4.
+---
+name:            latch_vs_exiting_no_sink
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: latch_vs_exiting_no_sink
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $p0, $r0, $r1, $dm0, $s0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:er = COPY $r0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:ep = COPY $p0
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:er = COPY $r1
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:edm = COPY $dm0
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:es = COPY $s0
+  ; CHECK-NEXT:   PseudoJ_jump_imm %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   $srssign0 = COPY [[COPY2]]
+  ; CHECK-NEXT:   PseudoJ_jump_imm %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   successors: %bb.3(0x7c000000), %bb.4(0x04000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[VSRS_4x_mv_x_srs_dm_srsSign0_:%[0-9]+]]:mxs = VSRS_4x_mv_x_srs_dm_srsSign0 [[COPY3]], [[COPY4]], implicit-def $srsrs_of, implicit $crrnd, implicit $crsrsmode, implicit $crsat, implicit $srssign0
+  ; CHECK-NEXT:   PseudoJNZ [[COPY]], %bb.3
+  ; CHECK-NEXT:   PseudoJ_jump_imm %bb.4
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   $srssign0 = MOVX_mvx_cr_imm 0
+  ; CHECK-NEXT:   PseudoJ_jump_imm %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4:
+  ; CHECK-NEXT:   PseudoRET implicit $lr
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $p0, $r0, $r1, $dm0, $s0
+    %0:er = COPY $r0
+    %1:ep = COPY $p0
+    %2:er = COPY $r1
+    %3:edm = COPY $dm0
+    %4:es = COPY $s0
+    PseudoJ_jump_imm %bb.1
+
+  bb.1:
+    successors: %bb.2(0x80000000)
+    $srssign0 = COPY %2
+    PseudoJ_jump_imm %bb.2
+
+  bb.2:
+    successors: %bb.3(0x7c000000), %bb.4(0x04000000)
+    %5:mxs = VSRS_4x_mv_x_srs_dm_srsSign0 %3, %4, implicit-def $srsrs_of, implicit $crrnd, implicit $crsrsmode, implicit $crsat, implicit $srssign0
+    PseudoJNZ %0, %bb.3
+    PseudoJ_jump_imm %bb.4
+
+  bb.3:
+    successors: %bb.1(0x80000000)
+    $srssign0 = MOVX_mvx_cr_imm 0
+    PseudoJ_jump_imm %bb.1
+
+  bb.4:
+    PseudoRET implicit $lr
+...
+
 # $srssign0 is used in one conditional branch (bb.2) but defined in the other
 # (bb.3). The latch (bb.4) defines $srssign0 = MOVX 0 without using it first,
 # so LatchEntryLive does NOT flag it. However, $srssign0 IS a true loop livein