[InstCombine][AIEX] Add load->trunc->inttoptr combine pattern

InstCombine optimization for load->trunc->inttoptr pattern on aie
The aie target has 20-bit pointers, which are stored as i24 (3 bytes)
This optimization converts: load i24 -> trunc i20 -> inttoptr
Into: load ptr -> ptrtoint -> zext i24
This allows SROA to recognize pointer-only allocas and promote them

Author: andcarminati

clang/test/CodeGen/aie/aie2p/aie2p-stream-intrinsics.cpp

@@ -4,7 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// Modifications (c) Copyright 2024 Advanced Micro Devices, Inc. or its
+// Modifications (c) Copyright 2024-2026 Advanced Micro Devices, Inc. or its
 // affiliates
 //
 //===----------------------------------------------------------------------===//
@@ -987,6 +987,98 @@ static bool canSimplifyNullStoreOrGEP(StoreInst &SI) {
           !NullPointerIsDefined(SI.getFunction(), SI.getPointerAddressSpace()));
 }
 
+/// Optimize loads that feed trunc->inttoptr patterns on targets with
+/// non-byte-aligned pointer sizes.
+///
+/// Pattern: load iN -> trunc iM -> inttoptr ptr (where iM is pointer size)
+/// Transform: load iN -> (zext (ptrtoint (load ptr)))
+///
+/// This transformation is only applied when all uses of the load only
+/// access the low PtrSize bits, ensuring the transformation is safe.
+///
+/// Safety is verified by checking each use:
+/// - Truncations to PtrSize or smaller bits are safe
+/// - And operations with masks that don't touch upper bits are safe
+/// - Other uses are conservatively rejected
+///
+/// Note: We manually check specific patterns rather than using DemandedBits
+/// analysis because DemandedBits/SimplifyDemandedBits would modify the IR,
+/// and we need a read-only check here. This approach could be extended to
+/// handle additional safe patterns in the future (e.g., shifts, specific
+/// arithmetic operations with known ranges).
+///
+/// \returns the replacement value if optimization was applied, nullptr
+/// otherwise.
+static Value *foldLoadWithTruncIntToPtrPattern(InstCombinerImpl &IC,
+                                               LoadInst &LI) {
+  if (!LI.getType()->isIntegerTy())
+    return nullptr;
+
+  const unsigned LoadWidth = LI.getType()->getIntegerBitWidth();
+  const unsigned AS = LI.getPointerAddressSpace();
+  const DataLayout &DL = IC.getDataLayout();
+  const unsigned PtrSize = DL.getPointerSizeInBits(AS);
+
+  // Check if pattern exists: trunc to PtrSize -> inttoptr
+  bool HasPattern = false;
+  for (const User *U : LI.users()) {
+    if (const auto *Trunc = dyn_cast<TruncInst>(U)) {
+      if (Trunc->getDestTy()->getIntegerBitWidth() == PtrSize) {
+        for (const User *TU : Trunc->users()) {
+          if (isa<IntToPtrInst>(TU)) {
+            HasPattern = true;
+            break;
+          }
+        }
+      }
+    }
+    if (HasPattern)
+      break;
+  }
+
+  if (!HasPattern)
+    return nullptr;
+
+  // Safety check: verify all uses only need low PtrSize bits
+  const APInt UpperBitsMask =
+      APInt::getHighBitsSet(LoadWidth, LoadWidth - PtrSize);
+
+  for (const User *LoadUser : LI.users()) {
+    // Trunc to PtrSize or smaller is safe
+    if (const auto *T = dyn_cast<TruncInst>(LoadUser)) {
+      if (T->getDestTy()->getIntegerBitWidth() > PtrSize)
+        return nullptr; // Early return: unsafe trunc
+      continue;
+    }
+
+    // And with mask that doesn't touch upper bits is safe
+    if (const auto *And = dyn_cast<BinaryOperator>(LoadUser)) {
+      if (And->getOpcode() == Instruction::And) {
+        if (const auto *C = dyn_cast<ConstantInt>(And->getOperand(1))) {
+          if ((C->getValue() & UpperBitsMask).isZero())
+            continue; // Safe
+        }
+      }
+    }
+
+    // Other uses - conservatively reject
+    return nullptr; // Early return: unsafe use
+  }
+
+  // All checks passed - apply transformation
+  Type *PtrTy = PointerType::get(LI.getContext(), AS);
+  LoadInst *PtrLoad =
+      new LoadInst(PtrTy, LI.getPointerOperand(), LI.getName(), LI.isVolatile(),
+                   LI.getAlign(), LI.getOrdering(), LI.getSyncScopeID());
+  PtrLoad->setDebugLoc(LI.getDebugLoc());
+  PtrLoad->copyMetadata(LI);
+  IC.InsertNewInstWith(PtrLoad, LI.getIterator());
+
+  Value *PtrToInt = IC.Builder.CreatePtrToInt(
+      PtrLoad, IntegerType::get(LI.getContext(), PtrSize));
+  return IC.Builder.CreateZExt(PtrToInt, LI.getType());
+}
+
 static bool canSimplifyNullLoadOrGEP(LoadInst &LI, Value *Op) {
   if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(Op)) {
     const Value *GEPI0 = GEPI->getOperand(0);
@@ -1002,6 +1094,10 @@ static bool canSimplifyNullLoadOrGEP(LoadInst &LI, Value *Op) {
 }
 
 Instruction *InstCombinerImpl::visitLoadInst(LoadInst &LI) {
+  // Optimize integer loads that feed trunc->inttoptr pattern
+  if (Value *V = foldLoadWithTruncIntToPtrPattern(*this, LI))
+    return replaceInstUsesWith(LI, V);
+
   Value *Op = LI.getOperand(0);
   if (Value *Res = simplifyLoadInst(&LI, Op, SQ.getWithInstruction(&LI)))
     return replaceInstUsesWith(LI, Res);

clang/test/CodeGen/aie/common-tests/aie-stream-intrinsics.cpp

@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+;
+; This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+;
+; (c) Copyright 2026 Advanced Micro Devices, Inc. or its affiliates
+;
+; RUN: opt -S -passes=instcombine -mtriple=aie2p %s | FileCheck %s
+; RUN: opt -S -passes=instcombine -mtriple=aie2ps %s | FileCheck %s
+
+; Test InstCombine optimization for load->trunc->inttoptr pattern on aie
+; The aie target has 20-bit pointers, which are stored as i24 (3 bytes)
+; This optimization converts: load i24 -> trunc i20 -> inttoptr
+; Into: load ptr -> ptrtoint -> zext i24
+; This allows SROA to recognize pointer-only allocas and promote them
+
+; Basic test: load i24 -> trunc i20 -> inttoptr should be optimized
+define ptr @test_load_trunc_inttoptr_basic(ptr %p) {
+; CHECK-LABEL: @test_load_trunc_inttoptr_basic(
+; CHECK-NEXT:    [[LOAD12:%.*]] = load ptr, ptr [[P:%.*]], align 4
+; CHECK-NEXT:    ret ptr [[LOAD12]]
+;
+  %load = load i24, ptr %p, align 4
+  %trunc = trunc i24 %load to i20
+  %ptr = inttoptr i20 %trunc to ptr
+  ret ptr %ptr
+}
+
+; Test with safe additional use (and with small mask that doesn't touch upper bits)
+define ptr @test_load_trunc_inttoptr_with_and(ptr %p) {
+; CHECK-LABEL: @test_load_trunc_inttoptr_with_and(
+; CHECK-NEXT:    [[LOAD12:%.*]] = load ptr, ptr [[P:%.*]], align 4
+; CHECK-NEXT:    ret ptr [[LOAD12]]
+;
+  %load = load i24, ptr %p, align 4
+  %and = and i24 %load, 31  ; Only uses low 5 bits - safe
+  %trunc = trunc i24 %load to i20
+  %ptr = inttoptr i20 %trunc to ptr
+  ret ptr %ptr
+}
+
+; Test with multiple safe truncs (all to <= 20 bits)
+define ptr @test_load_trunc_inttoptr_multiple_safe_truncs(ptr %p) {
+; CHECK-LABEL: @test_load_trunc_inttoptr_multiple_safe_truncs(
+; CHECK-NEXT:    [[LOAD12:%.*]] = load ptr, ptr [[P:%.*]], align 4
+; CHECK-NEXT:    ret ptr [[LOAD12]]
+;
+  %load = load i24, ptr %p, align 4
+  %trunc1 = trunc i24 %load to i16  ; Safe: 16 <= 20
+  %trunc2 = trunc i24 %load to i20  ; Safe: 20 <= 20
+  %ptr = inttoptr i20 %trunc2 to ptr
+  ret ptr %ptr
+}
+
+; Negative test: unsafe trunc (> 20 bits) should prevent optimization
+define i22 @test_load_trunc_inttoptr_unsafe_trunc(ptr %p) {
+; CHECK-LABEL: @test_load_trunc_inttoptr_unsafe_trunc(
+; CHECK-NEXT:    [[LOAD:%.*]] = load i24, ptr [[P:%.*]], align 4
+; CHECK-NEXT:    [[TRUNC_UNSAFE:%.*]] = trunc i24 [[LOAD]] to i22
+; CHECK-NEXT:    ret i22 [[TRUNC_UNSAFE]]
+;
+  %load = load i24, ptr %p, align 4
+  %trunc_unsafe = trunc i24 %load to i22  ; Unsafe: 22 > 20
+  %trunc = trunc i24 %load to i20
+  %ptr = inttoptr i20 %trunc to ptr
+  ret i22 %trunc_unsafe  ; Use the unsafe trunc
+}
+
+; Negative test: and with mask that touches upper bits should prevent optimization
+define i24 @test_load_trunc_inttoptr_unsafe_and(ptr %p) {
+; CHECK-LABEL: @test_load_trunc_inttoptr_unsafe_and(
+; CHECK-NEXT:    [[LOAD:%.*]] = load i24, ptr [[P:%.*]], align 4
+; CHECK-NEXT:    ret i24 [[LOAD]]
+;
+  %load = load i24, ptr %p, align 4
+  %and = and i24 %load, 16777215  ; Uses all 24 bits including upper bits
+  %trunc = trunc i24 %load to i20
+  %ptr = inttoptr i20 %trunc to ptr
+  ret i24 %and  ; Use the and result
+}
+
+; Negative test: other use type should prevent optimization
+define i24 @test_load_trunc_inttoptr_other_use(ptr %p) {
+; CHECK-LABEL: @test_load_trunc_inttoptr_other_use(
+; CHECK-NEXT:    [[LOAD:%.*]] = load i24, ptr [[P:%.*]], align 4
+; CHECK-NEXT:    [[ADD:%.*]] = add i24 [[LOAD]], 1
+; CHECK-NEXT:    ret i24 [[ADD]]
+;
+  %load = load i24, ptr %p, align 4
+  %add = add i24 %load, 1  ; Unknown use - conservatively unsafe
+  %trunc = trunc i24 %load to i20
+  %ptr = inttoptr i20 %trunc to ptr
+  ret i24 %add  ; Use the add result
+}

llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp

@@ -1,4 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+;
+; Modifications (c) Copyright 2024-2026 Advanced Micro Devices, Inc. or its
+; affiliates
+
 ; RUN: opt -passes='instcombine<no-verify-fixpoint>' -S  < %s | FileCheck %s
 
 ; In many of these tests nuw can be inferred on the sunk GEP in the exit
@@ -373,15 +381,8 @@ declare i32 @__gxx_personality_v0(...)
 define i1 @test8(ptr %in, i64 %offset) {
 ; CHECK-LABEL: @test8(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[LD:%.*]] = load i64, ptr [[IN:%.*]], align 8
-; CHECK-NEXT:    [[TMP0:%.*]] = trunc i64 [[LD]] to i32
-; CHECK-NEXT:    [[CASTI8:%.*]] = inttoptr i32 [[TMP0]] to ptr
-; CHECK-NEXT:    [[TMP1:%.*]] = trunc i64 [[OFFSET:%.*]] to i32
-; CHECK-NEXT:    [[GEPI8:%.*]] = getelementptr inbounds i8, ptr [[CASTI8]], i32 [[TMP1]]
-; CHECK-NEXT:    [[TMP2:%.*]] = trunc i64 [[LD]] to i32
-; CHECK-NEXT:    [[PTRCAST:%.*]] = inttoptr i32 [[TMP2]] to ptr
-; CHECK-NEXT:    [[GEPI32:%.*]] = getelementptr inbounds nuw i8, ptr [[PTRCAST]], i32 4
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq ptr [[GEPI32]], [[GEPI8]]
+; CHECK-NEXT:    [[TMP2:%.*]] = trunc i64 [[LD:%.*]] to i32
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP2]], 4
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
 entry:

llvm/test/CodeGen/AIE/opt/load-trunc-inttoptr-fold.ll

@@ -4,7 +4,7 @@
 ; See https://llvm.org/LICENSE.txt for license information.
 ; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 ;
-; Modifications (c) Copyright 2024 Advanced Micro Devices, Inc. or its
+; Modifications (c) Copyright 2024-2026 Advanced Micro Devices, Inc. or its
 ; affiliates
 
 ; RUN: opt -passes=instcombine -S < %s | FileCheck %s
@@ -15,8 +15,7 @@ target datalayout = "p:32:32:32"
 define ptr @test1(ptr %x) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[B1:%.*]] = load i32, ptr [[X:%.*]], align 4
-; CHECK-NEXT:    [[C:%.*]] = inttoptr i32 [[B1]] to ptr
+; CHECK-NEXT:    [[C:%.*]] = load ptr, ptr [[X:%.*]], align 4
 ; CHECK-NEXT:    ret ptr [[C]]
 ;
 entry:

llvm/test/Transforms/InstCombine/indexed-gep-compares.ll

@@ -4,7 +4,7 @@
 ; See https://llvm.org/LICENSE.txt for license information.
 ; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 ;
-; (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
+; (c) Copyright 2024-2026 Advanced Micro Devices, Inc. or its affiliates
 
 ; RUN: opt -passes=instcombine -S < %s | FileCheck %s
 
@@ -26,8 +26,7 @@ entry:
 define ptr @load_intPtrType_to_ptr(ptr %x) {
 ; CHECK-LABEL: @load_intPtrType_to_ptr(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[B1:%.*]] = load i20, ptr [[X:%.*]], align 4
-; CHECK-NEXT:    [[C:%.*]] = inttoptr i20 [[B1]] to ptr
+; CHECK-NEXT:    [[C:%.*]] = load ptr, ptr [[X:%.*]], align 4
 ; CHECK-NEXT:    ret ptr [[C]]
 ;
 entry: