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[AIE2PS] Add RA-level test for 512-bit acc/vec spilling
Mirror llvm/test/CodeGen/AIE/aie2p/ra/spill-vec-acc.mir for aie2ps. The test runs the full register-allocation pipeline (greedy + virtregrewriter) on a kernel that builds an acc1024 in BB0, broadcasts many vec512 values, and consumes them across a tight self-loop in BB1. Without a combined acc/vec spill class the allocator must spill at least one 512-bit value to the stack; the captured CHECK lines show the resulting VST_X_SPILL / VLDA_X_SPILL traffic against %stack.0. This baseline establishes the pre-feature behavior so the upcoming combined spill class change can be measured by a CHECK-line diff (memory spill -> cross-bank allocation).
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‎llvm/test/CodeGen/AIE/aie2ps/ra/spill-vec-acc.mir‎

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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#
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# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
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# See https://llvm.org/LICENSE.txt for license information.
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# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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#
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# (c) Copyright 2026 Advanced Micro Devices, Inc. or its affiliates
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# RUN: llc -mtriple=aie2ps -verify-machineinstrs --start-before=greedy --stop-after=virtregrewriter %s -o - | FileCheck %s
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# Register-pressure scenario where an ACC1024 value is built in BB0 and
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# consumed across a tight self-loop in BB1, while many VEC512 broadcasts
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# are also live across the loop edge. Without a combined acc/vec spill
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# class, the allocator must spill at least one of these 512-bit values
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# to the stack. The aie2p target solves this with the
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# spill_vec512_to_composite class; this test mirrors that scenario for
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# aie2ps so that enabling the same combined class can be measured by a
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# CHECK-line diff (memory spill -> cross-bank allocation).
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---
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name: spill-vec-acc
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alignment: 16
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legalized: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: spill-vec-acc
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $r16 = MOV_RLC_imm11_pseudo 0
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; CHECK-NEXT: renamable $x5 = VBCST_32 renamable $r16
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; CHECK-NEXT: renamable $r0 = MOVXM_lng_cg -19312
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; CHECK-NEXT: renamable $x0 = VBCST_16 killed renamable $r0
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; CHECK-NEXT: VST_X_SPILL killed renamable $x0, %stack.0, implicit $sp :: (store (s512) into %stack.0)
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; CHECK-NEXT: renamable $r0 = MOVXM_lng_cg -19360
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; CHECK-NEXT: renamable $x2 = VBCST_16 killed renamable $r0
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; CHECK-NEXT: renamable $r0 = MOVXM_lng_cg -19424
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; CHECK-NEXT: renamable $x4 = VBCST_16 killed renamable $r0
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; CHECK-NEXT: renamable $r0 = MOVXM_lng_cg 32704
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; CHECK-NEXT: renamable $x6 = VBCST_16 killed renamable $r0
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; CHECK-NEXT: renamable $r0 = MOVXM_lng_cg 16256
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; CHECK-NEXT: renamable $x8 = VBCST_16 killed renamable $r0
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; CHECK-NEXT: renamable $r0 = MOVXM_lng_cg 46208
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; CHECK-NEXT: renamable $x10 = VBCST_16 killed renamable $r0
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; CHECK-NEXT: renamable $r0 = MOVXM_lng_cg 46144
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; CHECK-NEXT: renamable $x1 = VBCST_16 killed renamable $r0
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; CHECK-NEXT: renamable $r0 = MOVXM_lng_cg 46080
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; CHECK-NEXT: renamable $x3 = VBCST_16 killed renamable $r0
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; CHECK-NEXT: renamable $r0 = MOVXM_lng_cg 45952
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; CHECK-NEXT: renamable $bmll0 = COPY killed renamable $x5
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; CHECK-NEXT: renamable $x5 = VBCST_16 killed renamable $r0
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; CHECK-NEXT: renamable $r0 = MOV_RLC_imm11_pseudo 1
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; CHECK-NEXT: renamable $x7 = VBCST_16 renamable $r16
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; CHECK-NEXT: renamable $bmlh0 = COPY renamable $bmll0
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; CHECK-NEXT: renamable $x9 = VBCST_16 killed renamable $r0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $cml0:0x000000000000000C, $r16, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $x11 = VCONV_bf16_fp32_mv_conv_mv_x_srs_bf16 renamable $cml0, implicit-def dead $srf2fflags, implicit $crf2fmask, implicit $crfpconvsat, implicit $crrnd
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; CHECK-NEXT: renamable $x0 = VLDA_X_SPILL %stack.0, implicit $sp :: (load (s512) from %stack.0)
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; CHECK-NEXT: renamable $r18 = VGE_bf16 renamable $x11, killed renamable $x0, implicit $crbf8conf, implicit $crfp8conf
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; CHECK-NEXT: renamable $x0 = VSEL_16 renamable $x7, renamable $x10, killed renamable $r18, implicit $crbf8conf, implicit $crfp8conf
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; CHECK-NEXT: renamable $r18 = VGE_bf16 renamable $x11, renamable $x2, implicit $crbf8conf, implicit $crfp8conf
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; CHECK-NEXT: renamable $r20 = VGE_bf16 renamable $x11, renamable $x4, implicit $crbf8conf, implicit $crfp8conf
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; CHECK-NEXT: renamable $r22 = VGE_bf16 renamable $x11, renamable $x6, implicit $crbf8conf, implicit $crfp8conf
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; CHECK-NEXT: renamable $r24 = VGE_bf16 killed renamable $x11, renamable $x8, implicit $crbf8conf, implicit $crfp8conf
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; CHECK-NEXT: renamable $x0 = VSEL_16 killed renamable $x0, renamable $x1, killed renamable $r18, implicit $crbf8conf, implicit $crfp8conf
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; CHECK-NEXT: renamable $x0 = VSEL_16 killed renamable $x0, renamable $x3, killed renamable $r20, implicit $crbf8conf, implicit $crfp8conf
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; CHECK-NEXT: renamable $x0 = VSEL_16 killed renamable $x0, renamable $x5, killed renamable $r22, implicit $crbf8conf, implicit $crfp8conf
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; CHECK-NEXT: renamable $x0 = VSEL_16 killed renamable $x0, renamable $x7, killed renamable $r24, implicit $crbf8conf, implicit $crfp8conf
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; CHECK-NEXT: renamable $x0 = VSEL_16 killed renamable $x0, renamable $x9, renamable $r16, implicit $crbf8conf, implicit $crfp8conf
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; CHECK-NEXT: renamable $r8 = MOV_RLC_imm11_pseudo 0
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; CHECK-NEXT: dead $dm1 = VMUL_f_vmul_bf_vmul_bf_core_X_X $x7, killed $x0, killed $r8, implicit-def dead $srfpflags, implicit $crbf8conf, implicit $crfp8conf, implicit $crfpmask
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; CHECK-NEXT: PseudoJ_jump_imm %bb.1
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bb.0:
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successors: %bb.1(0x80000000)
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%36:mrs16m = MOV_RLC_imm11_pseudo 0
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%40:vec512 = VBCST_32 %36
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%58:mrm = MOVXM_lng_cg -19312
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%4:vec512 = VBCST_16 %58
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%57:mrm = MOVXM_lng_cg -19360
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%7:vec512 = VBCST_16 %57
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%56:mrm = MOVXM_lng_cg -19424
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%10:vec512 = VBCST_16 %56
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%55:mrm = MOVXM_lng_cg 32704
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%13:vec512 = VBCST_16 %55
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%54:mrm = MOVXM_lng_cg 16256
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%16:vec512 = VBCST_16 %54
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%47:mrm = MOVXM_lng_cg 46208
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%21:vec512 = VBCST_16 %47
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%48:mrm = MOVXM_lng_cg 46144
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%24:vec512 = VBCST_16 %48
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%49:mrm = MOVXM_lng_cg 46080
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%27:vec512 = VBCST_16 %49
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%50:mrm = MOVXM_lng_cg 45952
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undef %1.sub_512_acc_lo:acc1024 = COPY %40
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%30:vec512 = VBCST_16 %50
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%51:mrm = MOV_RLC_imm11_pseudo 1
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%19:vec512 = VBCST_16 %36
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%1.sub_512_acc_hi:acc1024 = COPY %1.sub_512_acc_lo
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%34:vec512 = VBCST_16 %51
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bb.1:
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successors: %bb.1(0x80000000)
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%0:vec512 = VCONV_bf16_fp32_mv_conv_mv_x_srs_bf16 %1, implicit-def dead $srf2fflags, implicit $crf2fmask, implicit $crfpconvsat, implicit $crrnd
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%3:mrs16m = VGE_bf16 %0, %4, implicit $crbf8conf, implicit $crfp8conf
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%18:vec512 = VSEL_16 %19, %21, %3, implicit $crbf8conf, implicit $crfp8conf
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%6:mrs16m = VGE_bf16 %0, %7, implicit $crbf8conf, implicit $crfp8conf
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%9:mrs16m = VGE_bf16 %0, %10, implicit $crbf8conf, implicit $crfp8conf
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%12:mrs16m = VGE_bf16 %0, %13, implicit $crbf8conf, implicit $crfp8conf
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%15:mrs16m = VGE_bf16 %0, %16, implicit $crbf8conf, implicit $crfp8conf
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%23:vec512 = VSEL_16 %18, %24, %6, implicit $crbf8conf, implicit $crfp8conf
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%26:vec512 = VSEL_16 %23, %27, %9, implicit $crbf8conf, implicit $crfp8conf
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%29:vec512 = VSEL_16 %26, %30, %12, implicit $crbf8conf, implicit $crfp8conf
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%32:vec512 = VSEL_16 %29, %19, %15, implicit $crbf8conf, implicit $crfp8conf
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%33:vec512 = VSEL_16 %32, %34, %36, implicit $crbf8conf, implicit $crfp8conf
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%62:mrv8 = MOV_RLC_imm11_pseudo 0
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dead %61:edm = VMUL_f_vmul_bf_vmul_bf_core_X_X %19, %33, %62, implicit-def dead $srfpflags, implicit $crbf8conf, implicit $crfp8conf, implicit $crfpmask
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PseudoJ_jump_imm %bb.1
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