[AIE] `chess_storage(TM:...)` is silently ignored (no warning)

[hunhoffe]

A variable annotated chess_storage(TM : addr) — the chess idiom for tile-mapped storage accessed via st.tm/ld.tm — compiles cleanly under Peano but the annotation is silently dropped: the variable lands in .bss and uses ordinary st/ld. Since the qualifier affects correctness (address space / instruction), the silent drop is a porting footgun.

Reproducer

#include <cstdint>
static volatile uint32_t tm_reg chess_storage(TM : 0x80000);
extern "C" void flip(uint32_t v) { tm_reg = v; }   // expect st.tm

clang++ --target=aie2p-none-unknown-elf -O2 -c tm.cc -o tm.o

Observed (nightly 21.0.0.2026052701+9e603b76; same on aie2): rc=0, no warning; tm_reg in .bss (llvm-objdump -t); flip() emits st r0, [p0, #0], not st.tm.

Cause

chess_storage(...) is #defined empty in lib/clang/21/include/aiebase_chess.h:49, so the preprocessor deletes it. Fine for decorative chess_* stubs, but TM: changes correctness.

Suggested fix

Warn by default when a correctness-significant chess_storage (e.g. TM:) is dropped, pointing at the intrinsic alternative. (Requires the macro to expand to a frontend-visible attribute rather than nothing.)

Workaround

#include <aie2pintrin.h>     // aiev2intrin.h for Phoenix
write_tm(value, addr);       // st.tm
uint32_t v = read_tm(addr);  // ld.tm

Add __builtin_aie2p_sched_barrier() between consecutive TM stores (cf. #2346).

Severity: low (diagnostic quality, not a miscompile).