Migrate post-rebase tests to 3-dim DMA + repeat_count convention

Three tests added on main after this branch's base were not covered by
the original migration:

- dma_to_npu_subview_nd.mlir (#3121): cut dma_memcpy_nd operands from the
  4-dim [0,0,0,0]/[1,1,1,N] form to the 3 pure data dims.
- hw_repeat_optimization_test.mlir (#3115): refresh expected dma_start
  repeat_count values for the 0-means-once objectfifo convention (the
  lowering already emits repeat_count - 1; only the expectations, written
  under the prior 1-means-once form, were stale).
- memtile_padding_test.mlir: reorder buffer/lock CHECK lines to match the
  current declaration order; DMA dimensions were already correct.

Co-Authored-By: Claude Opus 4 (1M context) <noreply@anthropic.com>

Author: hunhoffe

test/Conversion/DmaToNpu/dma_to_npu_subview_nd.mlir

@@ -28,7 +28,7 @@ module {
         : memref<2x256xi32> to memref<256xi32, strided<[1], offset: 256>>
       %row_cast = memref.reinterpret_cast %row to offset: [0], sizes: [256], strides: [1]
         : memref<256xi32, strided<[1], offset: 256>> to memref<256xi32>
-      aiex.npu.dma_memcpy_nd (%row_cast[0, 0, 0, 0][1, 1, 1, 256][0, 0, 0, 1])
+      aiex.npu.dma_memcpy_nd (%row_cast[0, 0, 0][1, 1, 256][0, 0, 1])
         { metadata = @buffer_2d_1d, id = 0 : i64 } : memref<256xi32>
     }
     %tile_0_0 = aie.tile(0, 0)
@@ -53,7 +53,7 @@ module {
         : memref<4x8x32xi32> to memref<32xi32, strided<[1], offset: 608>>
       %row_cast = memref.reinterpret_cast %row to offset: [0], sizes: [32], strides: [1]
         : memref<32xi32, strided<[1], offset: 608>> to memref<32xi32>
-      aiex.npu.dma_memcpy_nd (%row_cast[0, 0, 0, 0][1, 1, 1, 32][0, 0, 0, 1])
+      aiex.npu.dma_memcpy_nd (%row_cast[0, 0, 0][1, 1, 32][0, 0, 1])
         { metadata = @buffer_3d_1d, id = 0 : i64 } : memref<32xi32>
     }
     %tile_0_0 = aie.tile(0, 0)
@@ -79,7 +79,7 @@ module {
         : memref<2x4x8x32xi32> to memref<32xi32, strided<[1], offset: 1632>>
       %row_cast = memref.reinterpret_cast %row to offset: [0], sizes: [32], strides: [1]
         : memref<32xi32, strided<[1], offset: 1632>> to memref<32xi32>
-      aiex.npu.dma_memcpy_nd (%row_cast[0, 0, 0, 0][1, 1, 1, 32][0, 0, 0, 1])
+      aiex.npu.dma_memcpy_nd (%row_cast[0, 0, 0][1, 1, 32][0, 0, 1])
         { metadata = @buffer_4d_1d, id = 0 : i64 } : memref<32xi32>
     }
     %tile_0_0 = aie.tile(0, 0)
@@ -104,7 +104,7 @@ module {
         : memref<2x512xbf16> to memref<512xbf16, strided<[1], offset: 512>>
       %row_cast = memref.reinterpret_cast %row to offset: [0], sizes: [512], strides: [1]
         : memref<512xbf16, strided<[1], offset: 512>> to memref<512xbf16>
-      aiex.npu.dma_memcpy_nd (%row_cast[0, 0, 0, 0][1, 1, 1, 512][0, 0, 0, 1])
+      aiex.npu.dma_memcpy_nd (%row_cast[0, 0, 0][1, 1, 512][0, 0, 1])
         { metadata = @buffer_bf16, id = 0 : i64 } : memref<512xbf16>
     }
     %tile_0_0 = aie.tile(0, 0)
@@ -133,7 +133,7 @@ module {
         to memref<256xi32, strided<[1], offset: 1536>>
       %row_cast = memref.reinterpret_cast %row to offset: [0], sizes: [256], strides: [1]
         : memref<256xi32, strided<[1], offset: 1536>> to memref<256xi32>
-      aiex.npu.dma_memcpy_nd (%row_cast[0, 0, 0, 0][1, 1, 1, 256][0, 0, 0, 1])
+      aiex.npu.dma_memcpy_nd (%row_cast[0, 0, 0][1, 1, 256][0, 0, 1])
         { metadata = @buffer_chain, id = 0 : i64 } : memref<256xi32>
     }
     %tile_0_0 = aie.tile(0, 0)

test/objectFifo-stateful-transform/dma_transformations/memtile_padding_test.mlir

@@ -12,10 +12,6 @@
     // CHECK: %{{.*}}tile_0_0 = aie.tile(0, 0)
     // CHECK: %{{.*}}tile_0_1 = aie.tile(0, 1)
     // CHECK: %{{.*}}tile_0_2 = aie.tile(0, 2)
-    // CHECK: %[[VAL_2:.*]] = aie.buffer(%{{.*}}tile_0_1) {sym_name = "objFifo_out1_cons_buff_0"} : memref<64x64xi8>
-    // CHECK: %[[VAL_3:.*]] = aie.buffer(%{{.*}}tile_0_1) {sym_name = "objFifo_out1_cons_buff_1"} : memref<64x64xi8>
-    // CHECK: %[[VAL_4:.*]] = aie.lock(%{{.*}}tile_0_1, 2) {init = 2 : i32, sym_name = "objFifo_out1_cons_prod_lock_0"}
-    // CHECK: %[[VAL_5:.*]] = aie.lock(%{{.*}}tile_0_1, 3) {init = 0 : i32, sym_name = "objFifo_out1_cons_cons_lock_0"}
     // CHECK: %[[VAL_6:.*]] = aie.buffer(%{{.*}}tile_0_2) {sym_name = "objFifo_out1_buff_0"} : memref<64x64xi8>
     // CHECK: %[[VAL_7:.*]] = aie.buffer(%{{.*}}tile_0_2) {sym_name = "objFifo_out1_buff_1"} : memref<64x64xi8>
     // CHECK: %[[VAL_8:.*]] = aie.lock(%{{.*}}tile_0_2, 2) {init = 2 : i32, sym_name = "objFifo_out1_prod_lock_0"}
@@ -24,6 +20,10 @@
     // CHECK: %[[VAL_11:.*]] = aie.buffer(%{{.*}}tile_0_2) {sym_name = "objFifo_in1_cons_buff_1"} : memref<64x64xi8>
     // CHECK: %[[VAL_12:.*]] = aie.lock(%{{.*}}tile_0_2, 0) {init = 2 : i32, sym_name = "objFifo_in1_cons_prod_lock_0"}
     // CHECK: %[[VAL_13:.*]] = aie.lock(%{{.*}}tile_0_2, 1) {init = 0 : i32, sym_name = "objFifo_in1_cons_cons_lock_0"}
+    // CHECK: %[[VAL_2:.*]] = aie.buffer(%{{.*}}tile_0_1) {sym_name = "objFifo_out1_cons_buff_0"} : memref<64x64xi8>
+    // CHECK: %[[VAL_3:.*]] = aie.buffer(%{{.*}}tile_0_1) {sym_name = "objFifo_out1_cons_buff_1"} : memref<64x64xi8>
+    // CHECK: %[[VAL_4:.*]] = aie.lock(%{{.*}}tile_0_1, 2) {init = 2 : i32, sym_name = "objFifo_out1_cons_prod_lock_0"}
+    // CHECK: %[[VAL_5:.*]] = aie.lock(%{{.*}}tile_0_1, 3) {init = 0 : i32, sym_name = "objFifo_out1_cons_cons_lock_0"}
     // CHECK: %[[VAL_14:.*]] = aie.buffer(%{{.*}}tile_0_1) {sym_name = "objFifo_in1_buff_0"} : memref<64x64xi8>
     // CHECK: %[[VAL_15:.*]] = aie.buffer(%{{.*}}tile_0_1) {sym_name = "objFifo_in1_buff_1"} : memref<64x64xi8>
     // CHECK: %[[VAL_16:.*]] = aie.lock(%{{.*}}tile_0_1, 0) {init = 2 : i32, sym_name = "objFifo_in1_prod_lock_0"}

test/objectFifo-stateful-transform/repeat_count/hw_repeat_optimization_test.mlir

@@ -14,10 +14,10 @@
 // When numBlocks == 1 and repeat_count > 1, the stateful transform generates
 // 1 BD with dma_start repeat_count instead of N identical BDs.
 
-// MemTile with repeat_count=3, depth=1: 1 BD + repeat_count=2
+// MemTile with repeat_count=3, depth=1: 1 BD + repeat_count=3
 // CHECK-LABEL: @memtile_hw_repeat
 // CHECK:       %memtile_dma
-// CHECK:         aie.dma_start(MM2S, 0, ^[[BD:.*]], ^{{.*}}, repeat_count = 2)
+// CHECK:         aie.dma_start(MM2S, 0, ^[[BD:.*]], ^{{.*}}, repeat_count = 3)
 // CHECK:       ^[[BD]]:
 // CHECK:         aie.dma_bd(
 // CHECK:         aie.next_bd ^[[BD]]
@@ -32,10 +32,10 @@ module @memtile_hw_repeat {
 
 // -----
 
-// Core tile with repeat_count=4, depth=1: 1 BD + repeat_count=3
+// Core tile with repeat_count=4, depth=1: 1 BD + repeat_count=4
 // CHECK-LABEL: @core_hw_repeat
 // CHECK:       %mem_0_2 = aie.mem
-// CHECK:         aie.dma_start(MM2S, 0, ^[[BD:.*]], ^{{.*}}, repeat_count = 3)
+// CHECK:         aie.dma_start(MM2S, 0, ^[[BD:.*]], ^{{.*}}, repeat_count = 4)
 // CHECK:       ^[[BD]]:
 // CHECK:         aie.dma_bd(
 // CHECK:         aie.next_bd ^[[BD]]