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MLIR-AIE compile fails before chesslink artifacts (main_core_*chesslinked.ll missing) when preparing AIE artifacts for V++ link with HLS

Status: Open.

#3119 In Xilinx/mlir-aie;

· vule20 opened on May 28, 2026

test/npu-xrt/memtile_dmas/* tests TDR on Phoenix (NPU1) — do these actually pass in CI?

triagedThis has been looked at and triagedThis has been looked at and triaged

Status: Open.

#3062 In Xilinx/mlir-aie;

· FIM43-Redeye opened on May 10, 2026

ObjectFIFO Feature Analysis & New Proposed Features

enhancementNew feature or requestNew feature or request

good first issueGood for newcomersGood for newcomers

help wantedExtra attention is neededExtra attention is needed

Status: Open.

#3050 In Xilinx/mlir-aie;

· hunhoffe opened on May 6, 2026

Mode-2 tracing (execution/inst_exec) has major documentation gaps

triagedThis has been looked at and triagedThis has been looked at and triaged

Status: Open.

#3047 In Xilinx/mlir-aie;

· FIM43-Redeye opened on May 5, 2026

bfloat16 GEMM results not equal to HIP GPU GEMM results

triagedThis has been looked at and triagedThis has been looked at and triaged

Status: Open.

#3032 In Xilinx/mlir-aie;

· MaoxinYee opened on Apr 14, 2026

·  

IRON 1.4

i8 vector arith.muli and arith.maxsi fail to lower on AIE2P

Status: Open.

#3027 In Xilinx/mlir-aie;

· erwei-xilinx opened on Apr 10, 2026

·  

IRON 1.4

Trace infrastructure improvement ideas

Status: Open.

#3013 In Xilinx/mlir-aie;

· yenjames opened on Mar 31, 2026

mobilenet v3 example design improvements

enhancementNew feature or requestNew feature or request

qualityImprove code quality: maintainability, cleanup, code reorganization.Improve code quality: maintainability, cleanup, code reorganization.

Status: Open.

#3009 In Xilinx/mlir-aie;

· jackl-xilinx opened on Mar 30, 2026

aiecc should reject unknown command-line arguments

Status: Open.

#2989 In Xilinx/mlir-aie;

· andrej opened on Mar 18, 2026

·  

IRON 1.4

Port placement to MLIR and placer enhancement

Status: Open.

#2864 In Xilinx/mlir-aie;

· yenjames opened on Feb 11, 2026

Using ::acquire_equal and ::release intrinsics for runtime-locking from inside kernel code instead of MLIR

Status: Open.

#2852 In Xilinx/mlir-aie;

· lstasytis opened on Feb 6, 2026

Packet header modification from within tile kernel code

Status: Open.

#2761 In Xilinx/mlir-aie;

· lstasytis opened on Dec 10, 2025