Fix dma_op.py BD dimensions; restore stale doc comment

test/python/dma_op.py used innermost size=1 on i16, a sub-word
contiguous run that the new shared verifier (correctly) rejects.
Make the innermost dim (2,1) so the BD is realizable.

Also move the BDDimLayoutAttr doc comment back above
isContiguousBDTransfer; it got separated when verifyBDSizesStrides
was inserted in between.

Co-Authored-By: Claude Opus 4 (1M context) <noreply@anthropic.com>

Author: hunhoffe

lib/Dialect/AIE/IR/AIEDialect.cpp

@@ -2196,9 +2196,6 @@ void DMABDOp::print(::mlir::OpAsmPrinter &printer) {
   printer.printOptionalAttrDict((*this)->getAttrs(), elidedAttrs);
 }
 
-// A BDDimLayoutAttr array (outermost-first) describes a contiguous row-major
-// scan when the innermost stride is 1 and each outer stride equals the product
-// of all inner sizes.  Used by both DMABDOp verification and canonicalization.
 mlir::LogicalResult xilinx::AIE::verifyBDSizesStrides(
     mlir::Operation *forOp, unsigned elemWidthBits,
     uint32_t addressGranularityBits, llvm::ArrayRef<int64_t> inputSizes,
@@ -2267,6 +2264,9 @@ mlir::LogicalResult xilinx::AIE::verifyBDSizesStrides(
   return success();
 }
 
+// A BDDimLayoutAttr array (outermost-first) describes a contiguous row-major
+// scan when the innermost stride is 1 and each outer stride equals the product
+// of all inner sizes.  Used by both DMABDOp verification and canonicalization.
 bool xilinx::AIE::isContiguousBDTransfer(llvm::ArrayRef<BDDimLayoutAttr> dims) {
   if (dims.empty())
     return true; // no ND layout = trivially contiguous

test/python/dma_op.py

@@ -37,7 +37,7 @@
 #    %memtile_dma_0_1 = aie.memtile_dma(%tile_0_1) {
 #      %0 = aie.dma(MM2S, 0) [{
 #        aie.use_lock(%lock_0_1_0, AcquireGreaterEqual)
-#        aie.dma_bd(%mem_A : memref<2x1xi16>, 0, 2, [<size = 1, stride = 1>, <size = 1, stride = 1>, <size = 1, stride = 1>, <size = 1, stride = 1>])
+#        aie.dma_bd(%mem_A : memref<2x1xi16>, 0, 2, [<size = 1, stride = 1>, <size = 1, stride = 1>, <size = 1, stride = 1>, <size = 2, stride = 1>])
 #        aie.use_lock(%lock_0_1, Release)
 #      }]
 #      aie.end
@@ -75,7 +75,7 @@ def dma_in_A_to_compute():
                         (1, 1),
                         (1, 1),
                         (1, 1),
-                        (1, 1),
+                        (2, 1),
                     ],
                 )
                 use_lock(prod_lock_mem_A, LockAction.Release)