66#
77"""Trace events enumerations for AIE architectures.
88
9- Available modules:
10- - aie: AIE1 architecture events
11- - aie2: AIE2/AIEML architecture events
12- - aie2p: AIE2P architecture events
9+ Event enums are sourced from the TableGen-generated Python bindings
10+ (aie.dialects._aie_enum_gen), which are produced from the same aie-rt
11+ headers that define the hardware event numbers.
12+
13+ Architecture-specific enums (CoreEventAIE2, etc.) are re-exported here
14+ under architecture-agnostic names (CoreEvent, etc.) for convenience.
15+ Use get_events_for_device() to select the correct architecture.
1316"""
17+
1418from enum import IntEnum
19+ from types import SimpleNamespace
1520import typing
1621
17- from . import aie
18- from . import aie2
19- from . import aie2p
20-
21- from .aie2 import (
22- CoreEvent ,
23- MemEvent ,
24- ShimTileEvent ,
25- MemTileEvent ,
22+ from aie .dialects ._aie_enum_gen import (
23+ CoreEventAIE ,
24+ MemEventAIE ,
25+ ShimTileEventAIE ,
26+ CoreEventAIE2 ,
27+ MemEventAIE2 ,
28+ ShimTileEventAIE2 ,
29+ MemTileEventAIE2 ,
30+ CoreEventAIE2P ,
31+ MemEventAIE2P ,
32+ ShimTileEventAIE2P ,
33+ MemTileEventAIE2P ,
2634)
2735
2836from aie .dialects .aie import WireBundle , DMAChannelDir
2937
38+ # Default to AIE2 for backwards compatibility
39+ CoreEvent = CoreEventAIE2
40+ MemEvent = MemEventAIE2
41+ ShimTileEvent = ShimTileEventAIE2
42+ MemTileEvent = MemTileEventAIE2
43+
3044
3145# We use the packet type field in the packet header to help differentiate the tile
3246# that the packet came from. Since packet types don't inherently have meaning, we
@@ -44,11 +58,26 @@ class PacketType(IntEnum):
4458
4559def get_events_for_device (device : str ):
4660 if "xcvc1902" in device :
47- return aie
61+ return SimpleNamespace (
62+ CoreEvent = CoreEventAIE ,
63+ MemEvent = MemEventAIE ,
64+ ShimTileEvent = ShimTileEventAIE ,
65+ MemTileEvent = None , # AIE1 has no mem tiles
66+ )
4867 elif "npu2p" in device :
49- return aie2p
68+ return SimpleNamespace (
69+ CoreEvent = CoreEventAIE2P ,
70+ MemEvent = MemEventAIE2P ,
71+ ShimTileEvent = ShimTileEventAIE2P ,
72+ MemTileEvent = MemTileEventAIE2P ,
73+ )
5074 else :
51- return aie2
75+ return SimpleNamespace (
76+ CoreEvent = CoreEventAIE2 ,
77+ MemEvent = MemEventAIE2 ,
78+ ShimTileEvent = ShimTileEventAIE2 ,
79+ MemTileEvent = MemTileEventAIE2 ,
80+ )
5281
5382
5483def _get_port_events (enum_class ):
@@ -68,9 +97,6 @@ class GenericEvent:
6897 def __init__ (
6998 self , code : typing .Union [CoreEvent , MemEvent , ShimTileEvent , MemTileEvent ]
7099 ):
71- # For backwards compatibility, allow integer as event
72- if isinstance (code , int ):
73- code = CoreEvent (code )
74100 self .code : typing .Union [CoreEvent , MemEvent , ShimTileEvent , MemTileEvent ] = code
75101
76102 def get_register_writes (self ):
@@ -118,9 +144,6 @@ def __init__(
118144 enum_class = None ,
119145 valid_codes = None ,
120146 ):
121- # For backwards compatibility, allow integer as event
122- if isinstance (code , int ) and enum_class :
123- code = enum_class (code )
124147 if valid_codes :
125148 assert code in valid_codes
126149
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