Declarative aiecc rewrite

Author: andrej

include/aie/Dialect/AIEX/AIEUtils.h

@@ -7,9 +7,12 @@
 
 #include "aie/Dialect/AIE/IR/AIEDialect.h"
 #include "mlir/Dialect/MemRef/IR/MemRef.h"
+#include "mlir/IR/BuiltinOps.h"
 #include "mlir/IR/Value.h"
 #include "llvm/ADT/DenseMap.h"
 
+#include "llvm/Support/raw_ostream.h"
+
 using namespace mlir;
 
 namespace xilinx {
@@ -57,5 +60,16 @@ LogicalResult emitUpdateBdAddressFromOffsetParameter(OpBuilder &builder,
                                                      Operation *bdOp,
                                                      BaseMemRefType bufType,
                                                      uint64_t registerAddr);
+
+// Emit the params.txt description of every `aiex.scratchpad_parameter` in
+// `moduleOp` (with their assigned `state_table_idx`/`kind`) to `os`.
+//
+// Format (one entry per line, easily parsed with std::ifstream >>):
+//   <num_parameters>
+//   <name> <state_table_idx> <type> <kind>
+//   ...
+// where kind is "core" (shift-2 encoded, for read_scratchpad_parameter) or
+// "addr" (raw, for offset_parameter on DMA ops).
+void emitScratchpadParamsFile(mlir::ModuleOp moduleOp, llvm::raw_ostream &os);
 }
 } // namespace xilinx

lib/Dialect/AIE/IR/AIEDialect.cpp

@@ -3092,7 +3092,13 @@ RuntimeSequenceOp::getForSymbolInDevice(DeviceOp deviceOp,
                                         llvm::StringRef symbol) {
   RuntimeSequenceOp runtimeSequenceOp;
   if (!symbol.size()) {
-    runtimeSequenceOp = *deviceOp.getOps<RuntimeSequenceOp>().begin();
+    auto range = deviceOp.getOps<RuntimeSequenceOp>();
+    if (range.begin() == range.end()) {
+      // No runtime sequence in the device; let the caller emit a diagnostic
+      // rather than dereferencing an end iterator (which crashes).
+      return nullptr;
+    }
+    runtimeSequenceOp = *range.begin();
   } else {
     Operation *maybeRuntimeSequenceOp =
         mlir::SymbolTable::lookupSymbolIn(deviceOp, symbol);

lib/Dialect/AIEX/Transforms/AIELowerScratchpadParameters.cpp

@@ -6,6 +6,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "aie/Dialect/AIE/IR/AIEDialect.h"
+#include "aie/Dialect/AIEX/AIEUtils.h"
 #include "aie/Dialect/AIEX/IR/AIEXDialect.h"
 #include "aie/Dialect/AIEX/Transforms/AIEXPasses.h"
 
@@ -264,15 +265,10 @@ struct AIELowerScratchpadParametersPass
     }
   }
 
-  // Emit a single params.txt for the whole module.
-  //
-  // Format (one entry per line, easily parsed with std::ifstream >>):
-  //   <num_parameters>
-  //   <name> <state_table_idx> <type> <kind>
-  //   ...
-  // where kind is "core" (shift-2 encoded, for read_scratchpad_parameter) or
-  // "addr" (raw, for offset_parameter on DMA ops).
-  LogicalResult emitParamsFile(ArrayRef<ScratchpadParameterOp> allParams) {
+  // Emit a single params.txt for the whole module to `outputParamsFile`.
+  // The actual serialization lives in the shared `emitScratchpadParamsFile`
+  // helper so the aiecc graph and this pass stay in sync.
+  LogicalResult emitParamsFile() {
     if (outputParamsFile.empty())
       return success();
 
@@ -284,18 +280,7 @@ struct AIELowerScratchpadParametersPass
              << outputParamsFile << "': " << ec.message();
     }
 
-    out << allParams.size() << "\n";
-    for (auto p : allParams) {
-      std::string typeStr;
-      llvm::raw_string_ostream os(typeStr);
-      p.getType().print(os);
-      StringRef kindStr = p.getKind().value() == ScratchpadParameterKind::Addr
-                              ? "addr"
-                              : "core";
-      out << p.getSymName() << " "
-          << static_cast<unsigned>(p.getStateTableIdx().value()) << " "
-          << typeStr << " " << kindStr << "\n";
-    }
+    emitScratchpadParamsFile(getOperation(), out);
     return success();
   }
 
@@ -445,7 +430,7 @@ struct AIELowerScratchpadParametersPass
     }
 
     // Step 5: emit the single params.txt for the module.
-    if (failed(emitParamsFile(allParams))) {
+    if (failed(emitParamsFile())) {
       return signalPassFailure();
     }
   }

lib/Dialect/AIEX/Utils/AIEUtils.cpp

@@ -201,3 +201,21 @@ LogicalResult AIEX::emitUpdateBdAddressFromOffsetParameter(
       /*buffer=*/nullptr, /*column=*/nullptr, /*row=*/nullptr);
   return success();
 }
+
+void AIEX::emitScratchpadParamsFile(ModuleOp moduleOp, llvm::raw_ostream &os) {
+  SmallVector<AIEX::ScratchpadParameterOp> allParams;
+  moduleOp.walk([&](AIEX::ScratchpadParameterOp p) { allParams.push_back(p); });
+
+  os << allParams.size() << "\n";
+  for (auto p : allParams) {
+    std::string typeStr;
+    llvm::raw_string_ostream ts(typeStr);
+    p.getType().print(ts);
+    StringRef kindStr =
+        p.getKind().value() == AIEX::ScratchpadParameterKind::Addr ? "addr"
+                                                                   : "core";
+    os << p.getSymName() << " "
+       << static_cast<unsigned>(p.getStateTableIdx().value()) << " " << typeStr
+       << " " << kindStr << "\n";
+  }
+}

programming_guide/compilation_stages.md

@@ -166,7 +166,7 @@ linked into the final xclbin.
 | `main_core_<col>_<row>.ld.script` | linker script Peano used to lay out that ELF |
 | `main_core_<col>_<row>.ll` | per-core LLVM IR before `opt` |
 | `main_core_<col>_<row>.opt.ll` | per-core LLVM IR after `opt` |
-| `main_core_<col>_<row>.peanohack.ll` | Peano workaround IR (vector-intrinsic fixups) |
+| `main_core_<col>_<row>.peano-compat.ll` | Peano-compatible IR (LLVM-23 features downgraded for Peano's opt/llc) |
 | `main_core_<col>_<row>.o` | per-core compiled object that links into the `.elf` |
 | `<kernel>.cc` | `ExternalFunction` kernel source, copied in for `clang` |
 | `<kernel>_<hash>.o` | `clang`'s compiled `.o` for that `ExternalFunction` |

python/utils/callabledesign.py

@@ -344,14 +344,19 @@ def __call__(self, *runtime_args, **runtime_kwargs):
             extra_key=compilable._generation_cache_key(),
         )
 
-        kernel = self._kernel_cache.get(cache_key) if compilable.use_cache else None
-        if kernel is not None and (
-            not Path(kernel.xclbin_path).is_file()
-            or not Path(kernel.insts_path).is_file()
-        ):
-            self._kernel_cache.pop(cache_key, None)
-            kernel = None
-        if kernel is None:
+        if compilable.use_cache and cache_key in self._kernel_cache:
+            kernel = self._kernel_cache[cache_key]
+            # Defend against an on-disk artifact being removed out from under a
+            # live in-memory cache entry (e.g. a caller clearing ~/.npu/cache
+            # between dispatches): recompile if either the cached xclbin or the
+            # instructions file is gone.
+            if not (
+                Path(kernel.xclbin_path).is_file() and Path(kernel.insts_path).is_file()
+            ):
+                kernel = self._compile_and_build_kernel(
+                    compilable, cache_key, trace_config
+                )
+        else:
             kernel = self._compile_and_build_kernel(compilable, cache_key, trace_config)
 
         tensor_args, remaining_scalars = compilable.split_runtime_args(

python/utils/compile/utils.py

@@ -213,6 +213,9 @@ def compile_mlir_module(
         args.extend(["--aie-generate-elf", f"--elf-name={elf_path}"])
     if work_dir:
         args.append(f"--tmpdir={work_dir}")
+        # Emit input_with_addresses.mlir into work_dir; the JIT DMA-size
+        # validator (parse_dma_sizes) and the trace parser read it from there.
+        args.append("--aie-generate-input-with-addresses")
     if verbose:
         args.append("--verbose")
     if options:

test/aiecc/buffers_xclbin.mlir

@@ -5,10 +5,11 @@
 //===----------------------------------------------------------------------===//
 
 // The host BO count is derived from the runtime_sequence argument count, so a
-// 6-argument sequence emits exactly bo0..bo5.
+// 6-argument sequence emits exactly bo0..bo5. Only the generated kernels JSON
+// metadata is inspected, so this runs the front-end without compiling cores.
 
 // RUN: %python aiecc.py -n --no-compile --no-link --aie-generate-xclbin %s
-// RUN: FileCheck %s --input-file=buffers_xclbin.mlir.prj/main_kernels.json
+// RUN: FileCheck %s --input-file=buffers_xclbin.mlir.prj/kernels_main.json
 
 // CHECK: "name": "bo0"
 // CHECK: "offset": "0x14"

test/aiecc/buffers_xclbin_few.mlir

@@ -5,7 +5,7 @@
 //===----------------------------------------------------------------------===//
 
 // RUN: %python aiecc.py -n --no-compile --no-link --aie-generate-xclbin %s
-// RUN: FileCheck %s --input-file=buffers_xclbin_few.mlir.prj/main_kernels.json
+// RUN: FileCheck %s --input-file=buffers_xclbin_few.mlir.prj/kernels_main.json
 
 // The host BO count is the runtime_sequence argument count, floored at 5 to
 // satisfy the NPU firmware command-chain (xrt::runlist) ABI. A 2-argument

test/aiecc/cpp_aie2p_target.mlir

@@ -9,16 +9,15 @@
 
 // Test AIE2P (Strix) target compilation
 
-// RUN: aiecc --no-xchesscc --no-xbridge --verbose %s | FileCheck %s
-
-// CHECK: Successfully parsed input file
-// CHECK: Found 1 AIE device
-// CHECK: Detected AIE target: AIE2p
-// CHECK: Running resource allocation pipeline in-memory
-// CHECK: Resource allocation pipeline completed successfully
-// CHECK: Running routing pipeline in-memory
-// CHECK: Compiling core (0, 2)
-// CHECK: Compilation completed successfully
+// RUN: aiecc --no-xchesscc --no-xbridge --aie-generate-npu-insts --aie-generate-xclbin --verbose %s 2>&1 | FileCheck %s
+
+// Pipeline coverage plus AIE2p target detection, verified via the aie2p
+// code-generation triple.
+// CHECK: ({{[0-9]+}}/{{[0-9]+}}) input.mlir
+// CHECK: ({{[0-9]+}}/{{[0-9]+}}) placed.mlir
+// CHECK: ({{[0-9]+}}/{{[0-9]+}}) input_physical.mlir
+// CHECK: exec:{{.*}}--march=aie2p
+// CHECK: wrote edge 'insts_
 
 module {
   aie.device(npu2) {