[AIEPlacer] Unify objectfifo + flow placement through Adjacency

Replaces the parallel `ConnectivityGroup` / DFS-grouping path with the
same `Adjacency` representation already used by buffer / lock / cascade
constraints (#3041, #3042, #3046, prior commit on this branch).

## Motivation

Before this commit, the placer maintained two independent
"tile-to-tile relation" representations:

1. `Adjacency` -- introduced for buffer/cascade/lock affinity. Pairwise
   edges + indexed lookup. Used for legality predicates.
2. `ConnectivityGroup` + bespoke `MapVector<LT, SetVector<LT>>` adjacency
   + manual DFS in `buildFlowGroups`. Used for centroid placement of
   mem/shim tiles near their core peers.

These do the same job (encode "what tiles are related") in different
shapes. With #3046 landed there's now exactly one canonical
representation; the legacy fifo path is the only thing left using the
parallel one.

## What changes

- New `buildObjectFifoAdjacency(objectFifos, objectFifoLinks) -> Adjacency`:
  emits one edge per `(producer, consumer_i)` pair. Linked fifos share
  an intermediate tile (link tile == consumer of every source fifo and
  producer of every destination fifo), so the natural edge emission
  already connects all sibling endpoints transitively through that
  shared tile -- no separate group-id machinery needed.
- New `buildFlowAdjacency(flows, pktFlows) -> Adjacency`: one edge per
  `aie.flow` `(src, dst)`; per `aie.packet_flow`, cross-product of its
  `aie.packet_source`s and `aie.packet_dest`s.
- New `placeNonCoreTileByCentroid(lt, adjacencies, channelRequirements)`:
  BFS through every supplied adjacency starting at `lt`, accumulating
  columns of placed `CoreTile` peers along the way; place at the
  rounded centroid (or the LTO's pinned column if set), respecting
  channel-requirement capacity. Walking through `LogicalTileOp` peers
  preserves the legacy ConnectivityGroup behaviour of seeing cores
  reachable transitively through intermediate mem/shim tiles.
- Phase 4 + Phase 5 in `place()` collapse into a single iteration over
  unplaced non-core LTOs, each calling the new placement function.

## Removals

- `struct ConnectivityGroup` (header)
- `buildObjectFifoGroups`, `buildFlowGroups`, `placeNonCoreTilesInGroup`
  (cpp + header)

## Behavior

Identical placements on all existing lit tests (10/10 in
`test/place-tiles/`, including the multi-fifo `edge_detect`,
linked-fifo, and flow-grouping cases). Channel-requirements path is
untouched -- it's a per-tile resource counter, fundamentally not a
pairwise relation, and rightfully stays as `DenseMap<Op*, pair<in, out>>`
outside Adjacency.

Net diff: -25 lines. The unified path is shorter than the parallel one
it replaces.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

Author: erwei-xilinx

include/aie/Dialect/AIE/Transforms/AIEPlacer.h

@@ -22,16 +22,6 @@ enum class PlacerType { SequentialPlacer };
 // maps logical tile operations to physical coordinates
 using PlacementResult = llvm::DenseMap<mlir::Operation *, TileID>;
 
-// A set of LogicalTileOps connected by some connectivity op (objectfifo,
-// flow, packet_flow, ...). `coreTiles` is used to compute the common column
-// for placing the group's `nonCoreTiles`. Both lists may contain duplicates
-// when a tile is referenced by multiple connectivity ops in the same group;
-// duplicates intentionally weight the common-column average.
-struct ConnectivityGroup {
-  llvm::SmallVector<LogicalTileOp, 4> coreTiles;
-  llvm::SmallVector<LogicalTileOp, 4> nonCoreTiles;
-};
-
 // Track available tiles and resource usage
 struct TileAvailability {
   std::vector<TileID> compTiles;
@@ -96,19 +86,6 @@ class SequentialPlacer : public Placer {
 
   void limitCoresPerColumn(int maxCoresPerCol, int numColumns);
 
-  void buildObjectFifoGroups(llvm::ArrayRef<ObjectFifoCreateOp> objectFifos,
-                             llvm::ArrayRef<ObjectFifoLinkOp> objectFifoLinks,
-                             llvm::SmallVectorImpl<ConnectivityGroup> &groups);
-
-  void buildFlowGroups(llvm::ArrayRef<FlowOp> flows,
-                       llvm::ArrayRef<PacketFlowOp> pktFlows,
-                       llvm::SmallVectorImpl<ConnectivityGroup> &groups);
-
-  mlir::LogicalResult placeNonCoreTilesInGroup(
-      const ConnectivityGroup &group,
-      const llvm::DenseMap<mlir::Operation *, std::pair<int, int>>
-          &channelRequirements);
-
   std::optional<TileID> findTileWithCapacity(int targetCol,
                                              std::vector<TileID> &tiles,
                                              int requiredInputChannels,
@@ -130,11 +107,14 @@ class SequentialPlacer : public Placer {
       llvm::SmallVector<ObjectFifoCreateOp> &objectFifos,
       llvm::SmallVector<ObjectFifoLinkOp> &objectFifoLinks);
 
-  // Per-LTO peer edges indexed by either endpoint. Used by both shared-L1
-  // buffer adjacency (memory affinity) and cascade adjacency (cardinal
-  // direction). `tileToEdges` indexes into `edges` only for `LogicalTileOp`
-  // endpoints (the ones the placer visits); `TileOp` peers contribute coords
-  // via `TileLike::tryGetCol`/`tryGetRow`.
+  // Per-LTO peer edges indexed by either endpoint. Single canonical
+  // tile-to-tile representation used for every placer relation: shared-L1
+  // buffer / lock affinity (memory-affinity legality), cascade adjacency
+  // (cardinal-direction legality), and objectfifo / flow / packet_flow
+  // connectivity (centroid placement of mem/shim tiles). `tileToEdges`
+  // indexes into `edges` only for `LogicalTileOp` endpoints (the ones the
+  // placer visits); `TileOp` peers contribute coords via
+  // `TileLike::tryGetCol`/`tryGetRow`.
   struct Adjacency {
     llvm::SmallVector<std::pair<TileLike, TileLike>, 4> edges;
     llvm::DenseMap<mlir::Operation *, llvm::SmallVector<unsigned, 2>>
@@ -182,6 +162,35 @@ class SequentialPlacer : public Placer {
   // destination.
   Adjacency buildCascadeAdjacency(llvm::ArrayRef<CascadeFlowOp> cascadeFlows);
 
+  // Connectivity edges from `aie.objectfifo`s. Each fifo emits edges from
+  // its producer tile to each consumer tile. Linked fifos do not need to be
+  // consulted: the link tile naturally appears as the consumer of every
+  // source fifo and the producer of every destination fifo, so per-fifo
+  // edge emission already connects all sibling endpoints transitively
+  // through that shared tile -- no separate group-id pass needed. Used for
+  // non-core (mem/shim) tile placement, not for legality checks -- an
+  // unplaced mem/shim LTO is placed near the centroid of its placed core
+  // peers (transitively reachable through these edges).
+  Adjacency
+  buildObjectFifoAdjacency(llvm::ArrayRef<ObjectFifoCreateOp> objectFifos);
+
+  // Connectivity edges from `aie.flow` and `aie.packet_flow`. For `aie.flow`,
+  // each op emits one (src, dst) edge. For `aie.packet_flow`, each op emits
+  // a cross-product of its `aie.packet_source`s and `aie.packet_dest`s.
+  Adjacency buildFlowAdjacency(llvm::ArrayRef<FlowOp> flows,
+                               llvm::ArrayRef<PacketFlowOp> pktFlows);
+
+  // Place a single non-core (mem/shim) `LogicalTileOp` at the column closest
+  // to the centroid of its placed core peers, where peers are reached by BFS
+  // through every adjacency in `connectivityAdjacencies`. Falls back to
+  // column 0 if the LTO has no placed core peers (e.g., a tile not mentioned
+  // by any fifo or flow). Honours the LTO's own column pin if set.
+  mlir::LogicalResult placeNonCoreTileByCentroid(
+      LogicalTileOp logicalTile,
+      llvm::ArrayRef<const Adjacency *> connectivityAdjacencies,
+      const llvm::DenseMap<mlir::Operation *, std::pair<int, int>>
+          &channelRequirements);
+
   // Generic adjacency predicate. `pred` returns true iff `(firstPos,
   // secondPos)` satisfies the constraint, where `first` and `second` are
   // `adjacency.edges[i].first` and `.second`. Unplaced peers without pin