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Additional parallel programming example updates (#2481)
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
1 parent 4ddf987 commit e399423

34 files changed

Lines changed: 1563 additions & 1348 deletions

‎aie_kernels/aie2/swiglu.cc‎

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//===- swiglu.cc --------------------------------------------*- C++
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//-*-===//
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//
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// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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// Copyright (C) 2025, Advanced Micro Devices, Inc.
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//
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//===-------------------------------------------------- --------===//
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#include "../aie_kernel_utils.h"
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#include <aie_api/aie.hpp>
14+
#include <lut_based_ops.h>
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#include <stdint.h>
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using namespace aie;
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void swiglu_tanh_approx_bf16(bfloat16 *restrict input_vector,
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bfloat16 *restrict weight_vector_1,
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bfloat16 *restrict weight_vector_2,
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bfloat16 *restrict output_vector,
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const int32_t vector_size) {
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event0();
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int num_elems = vector_size;
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auto it_in = aie::begin_restrict_vector<16>((bfloat16 *)input_vector);
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auto it_wt_1 = aie::begin_restrict_vector<16>((bfloat16 *)weight_vector_1);
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auto it_wt_2 = aie::begin_restrict_vector<16>((bfloat16 *)weight_vector_2);
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auto it_out = aie::begin_restrict_vector<16>((bfloat16 *)output_vector);
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aie::vector<bfloat16, 16> input;
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aie::vector<bfloat16, 16> weight_1;
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aie::vector<bfloat16, 16> weight_2;
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aie::vector<bfloat16, 16> output;
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aie::vector<bfloat16, 16> register_0_5 = aie::broadcast<bfloat16, 16>(0.5f);
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aie::vector<bfloat16, 16> register_1 = aie::broadcast<bfloat16, 16>(1.0f);
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AIE_PREPARE_FOR_PIPELINING
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AIE_LOOP_MIN_ITERATION_COUNT(16)
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for (int i = 0; i < num_elems; i += 16) {
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// Load input vector
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input = *it_in++;
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// Load weights
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weight_1 = *it_wt_1++;
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weight_2 = *it_wt_2++;
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// Compute the first part of the SWiGLU: x * w1
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aie::vector<bfloat16, 16> mul_input_weight_1 = aie::mul(input, weight_1);
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// Compute the second part of the SWiGLU: x * w2
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aie::vector<bfloat16, 16> mul_input_weight_2 = aie::mul(input, weight_2);
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// Compute tanh approximation
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aie::vector<bfloat16, 16> half_x =
54+
aie::mul(mul_input_weight_2, register_0_5);
55+
aie::vector<bfloat16, 16> tanh_half_x = getTanhBf16(half_x);
56+
auto tanh_half_x_approx = aie::add(tanh_half_x, register_1);
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aie::vector<bfloat16, 16> sigmoid_approx =
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aie::mul(tanh_half_x_approx, register_0_5);
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// Compute output: x * tanh_approx
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aie::vector<bfloat16, 16> silu_output =
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aie::mul(mul_input_weight_2, sigmoid_approx);
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// Multiply the first part with the second part
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auto mul_output = aie::mul(mul_input_weight_1, silu_output);
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// Store output vector
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*it_out++ = mul_output.to_vector<bfloat16>();
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}
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event1();
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return;
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}
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extern "C" {
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void swiglu_bf16(bfloat16 *restrict input, bfloat16 *restrict weights_1,
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bfloat16 *restrict weights_2, bfloat16 *restrict output) {
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int32_t input_size = 1024; // Assuming input size is a multiple of 16
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swiglu_tanh_approx_bf16(input, weights_1, weights_2, output, input_size);
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}
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} // extern "C"

‎aie_kernels/aie2p/swiglu.cc‎

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//===- swiglu.cc --------------------------------------------*- C++
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//-*-===//
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//
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// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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// Copyright (C) 2025, Advanced Micro Devices, Inc.
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//
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//===-------------------------------------------------- --------===//
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#include "../aie_kernel_utils.h"
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#include <aie_api/aie.hpp>
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#include <stdint.h>
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using namespace aie;
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void swiglu_tanh_approx_bf16(bfloat16 *restrict input_vector,
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bfloat16 *restrict weight_vector_1,
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bfloat16 *restrict weight_vector_2,
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bfloat16 *restrict output_vector,
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const int32_t vector_size) {
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event0();
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int num_elems = vector_size;
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auto it_in = aie::begin_restrict_vector<16>((bfloat16 *)input_vector);
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auto it_wt_1 = aie::begin_restrict_vector<16>((bfloat16 *)weight_vector_1);
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auto it_wt_2 = aie::begin_restrict_vector<16>((bfloat16 *)weight_vector_2);
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auto it_out = aie::begin_restrict_vector<16>((bfloat16 *)output_vector);
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aie::vector<bfloat16, 16> input;
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aie::vector<bfloat16, 16> weight_1;
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aie::vector<bfloat16, 16> weight_2;
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aie::vector<bfloat16, 16> output;
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aie::vector<bfloat16, 16> register_0_5 = aie::broadcast<bfloat16, 16>(0.5f);
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aie::vector<bfloat16, 16> register_1 = aie::broadcast<bfloat16, 16>(1.0f);
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AIE_PREPARE_FOR_PIPELINING
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AIE_LOOP_MIN_ITERATION_COUNT(16)
39+
for (int i = 0; i < num_elems; i += 16) {
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// Load input vector
41+
input = *it_in++;
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// Load weights
43+
weight_1 = *it_wt_1++;
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weight_2 = *it_wt_2++;
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// Compute the first part of the SWiGLU: x * w1
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aie::vector<bfloat16, 16> mul_input_weight_1 = aie::mul(input, weight_1);
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// Compute the second part of the SWiGLU: x * w2
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aie::vector<bfloat16, 16> mul_input_weight_2 = aie::mul(input, weight_2);
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// Compute tanh approximation
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auto half_x = aie::mul(mul_input_weight_2, register_0_5);
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auto tanh_half_x = aie::tanh<bfloat16>(half_x.to_vector<float>());
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auto tanh_half_x_approx = aie::add(tanh_half_x, register_1);
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aie::vector<bfloat16, 16> sigmoid_approx =
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aie::mul(tanh_half_x_approx, register_0_5);
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// Compute output: x * tanh_approx
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aie::vector<bfloat16, 16> silu_output =
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aie::mul(mul_input_weight_2, sigmoid_approx);
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// Multiply the first part with the second part
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auto mul_output = aie::mul(mul_input_weight_1, silu_output);
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// Store output vector
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*it_out++ = mul_output.to_vector<bfloat16>();
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}
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event1();
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return;
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}
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extern "C" {
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void swiglu_bf16(bfloat16 *restrict input, bfloat16 *restrict weights_1,
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bfloat16 *restrict weights_2, bfloat16 *restrict output) {
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int32_t input_size = 1024; // Assuming input size is a multiple of 16
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swiglu_tanh_approx_bf16(input, weights_1, weights_2, output, input_size);
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}
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} // extern "C"

‎programming_examples/ml/eltwise_add/CMakeLists.txt‎

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set(XRT_LIB_DIR C:/Technical/xrtNPUfromDLL CACHE STRING "Path to xrt_coreutil.lib")
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endif()
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set(IN1_SIZE 131072 CACHE STRING "in1 buffer size")
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set(IN2_SIZE 131072 CACHE STRING "in2 buffer size")
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set(OUT_SIZE 131072 CACHE STRING "out buffer size")
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set(TARGET_NAME test CACHE STRING "Target to be built")
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SET (ProjectName ${TARGET_NAME})
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project(${ProjectName})
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add_executable(${currentTarget}
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${CMAKE_CURRENT_SOURCE_DIR}/../../../runtime_lib/test_lib/test_utils.cpp
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test.cpp
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)
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target_compile_definitions(${currentTarget} PUBLIC
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IN1_SIZE=${IN1_SIZE}
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IN2_SIZE=${IN2_SIZE}
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OUT_SIZE=${OUT_SIZE}
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DISABLE_ABI_CHECK=1
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)
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target_compile_definitions(${currentTarget} PUBLIC DISABLE_ABI_CHECK=1)
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target_include_directories (${currentTarget} PUBLIC
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${XRT_INC_DIR}

‎programming_examples/ml/eltwise_add/Makefile‎

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include ${srcdir}/../../makefile-common
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VPATH := ${srcdir}/../../../aie_kernels/aie2
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all: build/final.xclbin
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devicename ?= $(if $(filter 1,$(NPU2)),npu2,npu)
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targetname = eltwise_add
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in1_size = 131072 # in bytes
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in2_size = 131072 # in bytes, should always be euqal to in1_size
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out_size = 131072 # in bytes, should always be equal to in1_size
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trace_size = 8192
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CHESS ?= false
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data_size = in1_size
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aie_py_src=${targetname}.py
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use_placed?=0
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ifeq (${use_placed}, 1)
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aie_py_src=${targetname}_placed.py
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endif
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all: build/final_${data_size}.xclbin build/insts_${data_size}.bin
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VPATH := ${srcdir}/../../../aie_kernels/aie2
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build/%.o: %.cc
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mkdir -p ${@D}
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ifeq ($(devicename),npu)
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cd ${@D} && ${PEANO_INSTALL_DIR}/bin/clang++ ${PEANOWRAP2_FLAGS} -c $< -o ${@F};
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cd ${@D} && ${PEANO_INSTALL_DIR}/bin/clang++ ${PEANOWRAP2_FLAGS} -c $< -o ${@F}
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else ifeq ($(devicename),npu2)
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cd ${@D} && ${PEANO_INSTALL_DIR}/bin/clang++ ${PEANOWRAP2P_FLAGS} -c $< -o ${@F};
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cd ${@D} && ${PEANO_INSTALL_DIR}/bin/clang++ ${PEANOWRAP2P_FLAGS} -c $< -o ${@F}
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else
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echo "Device type not supported"
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endif
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build/aie_${data_size}.mlir: ${srcdir}/${aie_py_src}
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build/aie.mlir: ${srcdir}/${aie_py_src}
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mkdir -p ${@D}
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python3 $< -d ${devicename} -i1s ${in1_size} -i2s ${in2_size} -os ${out_size} > $@
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python3 $< ${devicename} 0 > $@
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build/aie_trace_${data_size}.mlir: ${srcdir}/${aie_py_src}
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build/aie_trace.mlir: ${srcdir}/${aie_py_src}
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mkdir -p ${@D}
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python3 $< -d ${devicename} -i1s ${in1_size} -i2s ${in2_size} -os ${out_size} -t ${trace_size} > $@
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python3 $< ${devicename} ${trace_size} > $@
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build/final_${data_size}.xclbin: build/aie_${data_size}.mlir build/add.o
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build/final.xclbin: build/aie.mlir build/add.o
5444
mkdir -p ${@D}
55-
cd ${@D} && aiecc.py --aie-generate-xclbin --no-compile-host --xclbin-name=${@F} \
56-
--no-xchesscc --no-xbridge \
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--aie-generate-npu-insts --npu-insts-name=insts_${data_size}.bin $(<:%=../%)
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cd ${@D} && aiecc.py --aie-generate-xclbin --aie-generate-npu-insts --no-compile-host \
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--no-xchesscc --no-xbridge \
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--xclbin-name=${@F} --npu-insts-name=insts.bin ${<F}
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build/final_trace_${data_size}.xclbin: build/aie_trace_${data_size}.mlir build/add.o
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build/final_trace.xclbin: build/aie_trace.mlir build/add.o
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mkdir -p ${@D}
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cd ${@D} && aiecc.py --aie-generate-xclbin --no-compile-host --xclbin-name=${@F} \
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--no-xchesscc --no-xbridge \
63-
--aie-generate-npu-insts --npu-insts-name=insts_${data_size}.bin $(<:%=../%)
51+
cd ${@D} && aiecc.py --aie-generate-xclbin --aie-generate-npu-insts --no-compile-host \
52+
--no-xchesscc --no-xbridge \
53+
--xclbin-name=${@F} --npu-insts-name=insts.bin ${<F}
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${targetname}_${data_size}.exe: ${srcdir}/test.cpp
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${targetname}.exe: ${srcdir}/test.cpp
6657
rm -rf _build
6758
mkdir -p _build
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cd _build && ${powershell} cmake `${getwslpath} ${srcdir}` -DTARGET_NAME=${targetname}_${data_size} -DIN1_SIZE=${in1_size} -DIN2_SIZE=${in2_size} -DOUT_SIZE=${out_size}
59+
cd _build && ${powershell} cmake `${getwslpath} ${srcdir}` -DTARGET_NAME=${targetname}
6960
cd _build && ${powershell} cmake --build . --config Release
7061
ifeq "${powershell}" "powershell.exe"
71-
cp _build/${targetname}_${data_size}.exe $@
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cp _build/${targetname}.exe $@
7263
else
73-
cp _build/${targetname}_${data_size} $@
64+
cp _build/${targetname} $@
7465
endif
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run: ${targetname}_${data_size}.exe build/final_${data_size}.xclbin build/insts_${data_size}.bin
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${powershell} ./$< -x build/final_${data_size}.xclbin -i build/insts_${data_size}.bin -k MLIR_AIE
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trace: ${targetname}_${data_size}.exe build/final_trace_${data_size}.xclbin build/insts_${data_size}.bin
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${powershell} ./$< -x build/final_trace_${data_size}.xclbin -i build/insts_${data_size}.bin -k MLIR_AIE -t ${trace_size}
81-
${srcdir}/../../utils/parse_trace.py --input trace.txt --mlir build/aie_trace_${data_size}.mlir --output trace_${targetname}.json
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${srcdir}/../../utils/get_trace_summary.py --input trace_${targetname}.json
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trace_py: build/final_trace_${data_size}.xclbin build/insts_${data_size}.bin
85-
${powershell} python3 ${srcdir}/test.py -x build/final_trace_${data_size}.xclbin -i build/insts_${data_size}.bin -k MLIR_AIE -t ${trace_size} -i1s ${in1_size} -i2s ${in2_size} -os ${out_size}
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${srcdir}/../../utils/parse_trace.py --input trace.txt --mlir build/aie_trace_${data_size}.mlir --output trace_${targetname}.json
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${srcdir}/../../utils/get_trace_summary.py --input trace_${targetname}.json
67+
run: ${targetname}.exe build/final.xclbin
68+
${powershell} ./$< -x build/final.xclbin -i build/insts.bin -k MLIR_AIE
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89-
clean_trace:
90-
rm -rf tmpTrace trace.txt parse*json trace*json
70+
trace: ${targetname}.exe build/final_trace.xclbin
71+
${powershell} ./$< -x build/final_trace.xclbin -i build/insts.bin -k MLIR_AIE -t ${trace_size}
72+
${srcdir}/../../utils/parse_trace.py --input trace.txt --mlir build/aie_trace.mlir --output trace_eltwise_add.json
73+
${srcdir}/../../utils/get_trace_summary.py --input trace_eltwise_add.json
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92-
clean: clean_trace
93-
rm -rf build _build ${targetname}*.exe
75+
clean:
76+
rm -rf build _build ${targetname}.exe

‎programming_examples/ml/eltwise_add/README.md‎

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//
99
//===----------------------------------------------------------------------===//-->
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11-
# Eltwise Add
11+
# Eltwise Addition
1212

13-
This design implements a `bfloat16` based element wise addition between two vectors, performed in parallel on two cores in a single column. Element-wise addition usually ends up being I/O bound due to the low compute intensity. In a practical ML implementation, it is an example of the type of kernel that is likely best fused onto another more compute-dense kernel (e.g., a convolution or GEMM). Please refer to [bottleneck](../bottleneck/) design on fusing element-wise addition with convolution for the skip addition.
13+
This design implements a `bfloat16` based element-wise addtiplication between two vectors, performed in parallel on two cores in a single column. Element-wise addtiplication usually ends up being I/O bound due to the low compute intensity. In a practical ML implementation, it is an example of the type of kernel that is likely best fused onto another more compute-dense kernel (e.g., a convolution or GEMM).
1414

1515

1616
## Source Files Overview
1717

1818
1. `eltwise_add.py`: A Python script that defines the AIE array structural design using MLIR-AIE operations. This generates MLIR that is then compiled using `aiecc.py` to produce design binaries (ie. XCLBIN and inst.bin for the NPU in Ryzen™ AI).
1919

20-
1. `eltwise_add_placed.py`: An alternative version of the design in `eltwise_add.py`, that is expressed in a lower-level version of IRON.
21-
22-
1. `add.cc`: A C++ implementation of a vectorized vector addition operation for AIE cores. The code uses the AIE API, which is a C++ header-only library providing types and operations that get translated into efficient low-level intrinsics, and whose documentation can be found [here](https://www.xilinx.com/htmldocs/xilinx2023_2/aiengine_api/aie_api/doc/index.html). The source can be found [here](../../../aie_kernels/aie2/add.cc).
20+
1. `add.cc`: A C++ implementation of a vectorized vector addtiplication operation for AIE cores. The code uses the AIE API, which is a C++ header-only library providing types and operations that get translated into efficient low-level intrinsics, and whose documentation can be found [here](https://www.xilinx.com/htmldocs/xilinx2023_2/aiengine_api/aie_api/doc/index.html). The source can be found [here](../../../aie_kernels/aie2/add.cc).
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2422
1. `test.cpp`: This C++ code is a testbench for the design example. The code is responsible for loading the compiled XCLBIN file, configuring the AIE module, providing input data, and executing the AIE design on the NPU. After executing, the script verifies the memcpy results and optionally outputs trace data.
2523

@@ -33,18 +31,7 @@ To compile the design and C++ testbench:
3331
make
3432
```
3533

36-
To compile for the placed design:
37-
38-
```shell
39-
env use_placed=1 make
40-
```
41-
4234
To run the design:
4335
```shell
4436
make run
4537
```
46-
47-
To generate a [trace file](../../../programming_guide/section-4/section-4b/README.md):
48-
```shell
49-
env use_placed=1 make trace
50-
```

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