Merge branch 'phase0a-tct-token-balance' into dyn-seq-p3-aiex-to-emitc

Author: hunhoffe

.github/workflows/buildAndTestRyzenAISw.yml

@@ -141,7 +141,7 @@ jobs:
 
             ninja install
             # filter out slow tests (e.g. create-flows/vecmul_4x4_slow_test.mlir) due to timeout.
-            export LIT_OPTS="-j2 -sv --timeout 600 --filter-out slow_test"
+            export LIT_OPTS="-j1 -sv --timeout 600 --filter-out slow_test"
             ninja check-aie
 
             popd

.pre-commit-config.yaml

@@ -81,28 +81,27 @@ repos:
       files: ^(python/requirements_dev\.txt|utils/mlir_(aie_)?wheels/(requirements|ci-tools)\.(in|txt))$
 
     # REUSE compliance: every file must have a license/copyright notice (either
-    # inline or declared in REUSE.toml). Scans the whole repo, so it does not
-    # take filenames. Runs before check-copyright-format, which then validates
-    # the notice wording.
+    # inline or declared in REUSE.toml). Scoped to the files being pushed via
+    # `reuse lint-file` so an unrelated dirty working tree doesn't block a push;
+    # the authoritative whole-repo `reuse lint` still runs in CI. Runs before
+    # check-copyright-format, which then validates the notice wording.
     - id: reuse-lint
       name: Check REUSE compliance
       language: python
-      entry: reuse lint
+      entry: reuse lint-file
       additional_dependencies: ['reuse[charset-normalizer]==6.2.0']
-      pass_filenames: false
-      always_run: true
+      pass_filenames: true
       stages: [pre-push]
 
     # Format gate on top of REUSE: every copyright notice must match an approved
     # canonical form (see utils/check_copyright_format.py). REUSE only checks that
     # a notice exists, not how it is written, so this catches stray commas, the
-    # "AMD Inc." shorthand, "(c) Copyright" ordering, etc. Scans the whole repo
-    # via `reuse lint`, so it does not take filenames.
+    # "AMD Inc." shorthand, "(c) Copyright" ordering, etc. Scoped to the pushed
+    # files here; the script scans the whole repo when invoked with no args (CI).
     - id: check-copyright-format
       name: Check copyright notice format
       language: python
       entry: python utils/check_copyright_format.py
       additional_dependencies: ['reuse[charset-normalizer]==6.2.0']
-      pass_filenames: false
-      always_run: true
+      pass_filenames: true
       stages: [pre-push]

docs/AIEDesignPatterns.md

@@ -9,7 +9,7 @@ This document is an introduction to using the AIE dialect in practice and provid
 
 ## Using AIE Cores
 
-[Core Example](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/03_sync_with_locks/aie.mlir)
+[Core Example](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/aie/03_sync_with_locks/aie.mlir)
 
 We can use the AIE Cores as below to perform some operations
 
@@ -34,7 +34,7 @@ Perform some operations on the buffer in the core
 ```
 
 ## Single-buffered Communication
-[Single-buffer DMA example](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/05_tiledma/aie.mlir)
+[Single-buffer DMA example](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/aie/05_tiledma/aie.mlir)
 
 Define the AIE tiles you want to communicate between. Here Tile (7,1) will be the source and (7,2) the destination.
 
@@ -106,7 +106,7 @@ At the end, we release the lock back in state 0. This allows for the memory to r
 
 ## Double-buffered Communication
 
-[Double-buffer DMA example](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/17_shim_dma_with_core/aie.mlir)
+[Double-buffer DMA example](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/aie/17_shim_dma_with_core/aie.mlir)
 
 This example uses the same setup as the previous. For Tile (7,2) we can define an additional lock and buffer and change the buffers to be half the size:
 ```
@@ -158,7 +158,7 @@ We can use the core in a similar fashion, using the two locks to perform operati
 
 ## Controlling from the ARM Processor
 
-[Controlling From ARM](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/17_shim_dma_with_core/aie.mlir)
+[Controlling From ARM](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/aie/17_shim_dma_with_core/aie.mlir)
 
 We can perform some operations from the ARM processor and configure the lock to start the transfer. Here is a simple example where we write to a buffer, and begin the data transfer all from the host code.
 
@@ -220,7 +220,7 @@ XAieTile_LockRelease(&(TileInst[7][1]), 0, 1, 0); // Release lock
 This allows the data transfer to begin
 
 ## Static DDR Configuration
-[Static DDR](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/17_shim_dma_with_core/aie.mlir)
+[Static DDR](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/aie/17_shim_dma_with_core/aie.mlir)
 
 To read/write from DDR, we declare an external buffer with a location and size
 ```
@@ -237,7 +237,7 @@ We can then use the shim_dma to read/write from that location:
 	^bd0:
 		AIE.use_lock(%lock70 , "Acquire", 0)
 		AIE.dma_bd(%ext_buffer : memref<512xi32>, 0, 512)
-		AIE.use_lock(%lolock70 k72, "Release", 1)
+		AIE.use_lock(%lock70, "Release", 1)
 		br ^end 
 	^end:
 	AIE.end
@@ -348,7 +348,7 @@ XAieTile_LockRelease(&(TileInst[7][2]), 1, 0x1, 0);
 
 ## Using AIE ObjectFIFOs
 
-[ObjectFIFO Example](https://github.com/Xilinx/mlir-aie/tree/main/test/objectFifo-stateful-transform/non_adjacency_test_1.aie.mlir)
+[ObjectFIFO Example](https://github.com/Xilinx/mlir-aie/tree/main/test/objectFifo-stateful-transform/base/non_adjacency_test_1.mlir)
 
 An objectFIFO can be established between two or more tiles. Broadcast is possible from one producer tile to multiple consumer tiles.
 Unlike a typical FIFO, elements are not pushed to nor popped from the objectFIFO. Instead, a pool of memory elements is allocated to the objectFIFO by the objectFIFO lowering pass, i.e., AIEObjectFifoStatefulTransform.mlir. 
@@ -491,28 +491,9 @@ module @objectFIFO  {
 }
 ```
 
-At a higher abstraction level, a process can be registered to an objectFIFO using access patterns and work functions:
-```
-module @objectFIFO  {
-    %tile12 = AIE.tile(1, 2)
-    %tile33 = AIE.tile(3, 3)
-
-    AIE.objectfifo @of1 (%tile12, {tile33}, 2 : i32) : !AIE.objectfifo<memref<16xi32>>
-
-    %prodAcqPattern = arith.constant dense<[1]> : tensor<1xi32>
-    %prodRelPattern = arith.constant dense<[1]> : tensor<1xi32>
-    %prodLength = arith.constant 12 : index
-    func @producer_work() -> () {
-        return
-    }
-
-    AIE.objectfifo.register_process @of1 (Produce, %prodAcqPattern : tensor<1xi32>, %prodRelPattern : tensor<1xi32>, @producer_work, %prodLength)
-}
-```
-
 ## Using AIE broadcast_packet
 
-[broadcast_packet Example](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/23_broadcast_packet/aie.mlir)
+[broadcast_packet Example](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/aie/23_broadcast_packet/aie.mlir)
 
 The broadcast_packet operation is a logical connection that combines broadcast and packet-switch data transferring mechanism.
 

docs/AIEVectorization.md

@@ -8,7 +8,7 @@ Achieving high performance with the AIEngine architecture typically requires exe
 
 ## Affine Loops
 
-A typical starting point for automatic vectorization is to consider Affine looped programs. [Example](https://github.com/Xilinx/mlir-aie/tree/main/test/aievec/pointwise_mult_f32.mlir)
+A typical starting point for automatic vectorization is to consider Affine looped programs.
 ```
 func.func @pointwise_mult (%A: memref<2048xf32>, %B: memref<2048xf32>, %C: memref<2048xf32>) {
     affine.for %arg0 = 0 to 2048 {
@@ -71,7 +71,7 @@ aie-opt -affine-super-vectorize="virtual-vector-size=8 vectorize-reductions" --a
 
 This code can be translated to C++ code that can be included in a Vitis design:
 ```
-aie-opt -affine-super-vectorize="virtual-vector-size=8" --aie-vectorize < ../../aie/test/aievec/pointwise_mult_f32.mlir | aie-translate --aievec-to-cpp
+aie-opt -affine-super-vectorize="virtual-vector-size=8" --aie-vectorize < pointwise_mult_f32.mlir | aie-translate --aievec-to-cpp
 ```
 ```
 void pointwise_mult(float * restrict v1, float * restrict v2, float * restrict v3) {

docs/BuildingVersal.md

@@ -45,7 +45,7 @@ When targetting the VCK5000 Versal device, you must build and install our experi
 
 2. Source `utils/setup_python_packages.sh` to setup the prerequisite python
     packages. This script creates and installs the python packages
-    listed in `utils/requirements.txt` and `utils/requirements_dev.txt` in
+    listed in `python/requirements.txt` and `python/requirements_dev.txt` in
     a virtual python environment called 'sandbox', then it enters the sandbox:
     ```
     source utils/setup_python_packages.sh

docs/CMakeLists.txt

@@ -7,6 +7,18 @@ if (DOXYGEN_FOUND)
   set(abs_top_srcdir ${CMAKE_CURRENT_SOURCE_DIR})
   set(abs_top_builddir ${CMAKE_CURRENT_BINARY_DIR})
 
+  # Derive the project version from git tags (matches the wheel version) so the
+  # doxygen PROJECT_NUMBER stays accurate without hardcoding a release number.
+  execute_process(
+    COMMAND ${Python3_EXECUTABLE} ${AIE_SOURCE_DIR}/utils/mlir_aie_wheels/_version_helper.py
+    WORKING_DIRECTORY ${AIE_SOURCE_DIR}
+    OUTPUT_VARIABLE PACKAGE_VERSION
+    OUTPUT_STRIP_TRAILING_WHITESPACE
+    ERROR_QUIET)
+  if (NOT PACKAGE_VERSION)
+    set(PACKAGE_VERSION "unknown")
+  endif()
+
   if (HAVE_DOT)
     set(DOT ${LLVM_PATH_DOT})
   endif()
@@ -22,6 +34,7 @@ if (DOXYGEN_FOUND)
 
   set(abs_top_srcdir)
   set(abs_top_builddir)
+  set(PACKAGE_VERSION)
   set(DOT)
   set(enable_searchengine)
   set(searchengine_url)

docs/Devices.md

@@ -125,4 +125,4 @@ N Columns and 6 Rows
 
 -----
 
-<p align="center">Copyright&copy; 2024 AMD/Xilinx</p>
+<p align="center">Copyright&copy; 2024-2026 Advanced Micro Devices, Inc.</p>

docs/Platform.md

@@ -51,7 +51,7 @@ vck190 board + usb-c to usb cable + ethernet cable
 ## Board setup steps
 After the build is complete, format an SD card (16 GB+) in fat32 format and copy the files from the linux subdirectory onto the SD card.
 ```sh
-cp -r platforms/vck190_bare/petalinux/images/linux/* <SD card directory>
+cp -r platforms/vck190_bare_prod/petalinux/images/linux/* <SD card directory>
 ```
 Put the sd card into the micro sd slot to boot up the Versal device (top of the board), connect the board usb-c connector to your host machine and turn on the board. You should run a program like TeraTerm and configure it as a serial port (115200 baud, 8b data, no parity, 1b stop, no flow control). The serial port for Versal is usually the first port but may vary in your setup.
 
@@ -80,4 +80,4 @@ and run on the board as usual.
 
 -----
 
-<p align="center">Copyright&copy; 2019-2022 AMD/Xilinx</p>
+<p align="center">Copyright&copy; 2019-2021 Xilinx, Inc.<br>Copyright&copy; 2022-2026 Advanced Micro Devices, Inc.</p>

docs/Presentations.md

@@ -42,4 +42,4 @@
 </table>
 
 
-<p align="center">Copyright&copy; 2019-2022 AMD/Xilinx</p>
+<p align="center">Copyright&copy; 2019-2021 Xilinx, Inc.<br>Copyright&copy; 2022-2026 Advanced Micro Devices, Inc.</p>

docs/README.md

@@ -1,4 +1,5 @@
-<!-- Copyright (C) 2019-2024 Advanced Micro Devices, Inc. -->
+<!-- Copyright (C) 2019-2021 Xilinx, Inc. -->
+<!-- Copyright (C) 2022-2026 Advanced Micro Devices, Inc. -->
 <!-- SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -->
 # IRON API and MLIR-based AI Engine Toolchain
 
@@ -298,4 +299,4 @@ MLIR Tutorials
 
 -----
 
-<p align="center">Copyright&copy; 2019-2024 Advanced Micro Devices, Inc</p>
+<p align="center">Copyright&copy; 2019-2021 Xilinx, Inc.<br>Copyright&copy; 2022-2026 Advanced Micro Devices, Inc.</p>