MLIR-AIE compile fails before chesslink artifacts (main_core_*chesslinked.ll missing) when preparing AIE artifacts for V++ link with HLS

[vule20]

Title

MLIR-AIE compile fails before chesslink artifacts (main_core_*chesslinked.ll missing) when preparing AIE artifacts for V++ link with HLS

Environment

• OS: Linux
• Vitis: 2025.2
• Platform: /tools/Xilinx/2025.2/Vitis/base_platforms/xilinx_vck190_base_202520_1/xilinx_vck190_base_202520_1.xpfm
• Repo: mlir-aie (local workspace)
• Conda env: iron
• License present (AIEbuild, AIEsim)

Goal

Integrate:

• AIE kernel written in MLIR-AIE
• HLS PL data movers (mm2s, s2mm)
• v++ -l system link (hw_emu)

What works

• HLS kernels compile (v++ -c --mode hls ...) and link successfully with an ADF-C++ generated libadf.a.
• Tutorial mlir_exercises/tutorial-9 standard flow (make tutorial-9.exe) succeeds.

What fails

When compiling MLIR-AIE design standalone in custom integration folder, aiecc.py fails before generating chesslink outputs:

aiecc.py -j4 --sysroot=... --host-target=aarch64-linux-gnu aie_add10.mlir

Error:

chess-clang: error: no such file or directory: 'aie_add10.mlir.prj/main_core_1_4.chesslinked.ll'
chess-clang: error: no input files
xchesscc Failed Operation now in progress
Error running xchesscc_wrapper
Compilation failed

Observed outputs in .prj are only early-stage files (main_core_1_4.ll, main_core_1_1_4.chesshack.ll), no *.chesslinked.ll.

Minimal MLIR used

module @aie_add10 {
  aie.device(xcvc1902) {
    %tile14 = aie.tile(1, 4)
    %buf = aie.buffer(%tile14) { sym_name = "a14" } : memref<256xi32>
    %lock14_0 = aie.lock(%tile14, 0) { sym_name = "lock14_0" }

    func.func private @extern_kernel(%b: memref<256xi32>) -> ()
      attributes {link_with = "kernel.o"}

    %core14 = aie.core(%tile14) {
      aie.use_lock(%lock14_0, "Acquire", 0)
      func.call @extern_kernel(%buf) : (memref<256xi32>) -> ()
      aie.use_lock(%lock14_0, "Release", 1)
      aie.end
    }
  }
}

kernel.o is compiled with:

xchesscc ${CHESSCC_FLAGS} -c kernel.cc

Question

Is this a known issue in aiecc.py chess link stage / path resolution for MLIR-only flow in this environment?
What is the recommended flow to generate AIE artifacts from MLIR-AIE that are consumable by v++ -l with HLS kernels on VCK190 (2025.2)?

[fifield]

Question

Is this a known issue in aiecc.py chess link stage / path resolution for MLIR-only flow in this environment? What is the recommended flow to generate AIE artifacts from MLIR-AIE that are consumable by v++ -l with HLS kernels on VCK190 (2025.2)?

Artifacts from mlir-aie are not consumable by v++ as far as I know. At the very least that is not a supported or tested integration. However you should be able to program the PL with HLS in the usual ways then load the AIE array at runtime in Linux, with the two designs communicating over the Versal NoC, if communication between the two is the goal.