build(deps): bump llvm-project from 6fd5b8a to 89c6da2#275
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github-actions[bot] merged 1 commit intoApr 28, 2026
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Bumps [llvm-project](https://github.com/Xilinx/llvm-aie) from `6fd5b8a` to `89c6da2`. - [Release notes](https://github.com/Xilinx/llvm-aie/releases) - [Commits](Xilinx/llvm-aie@6fd5b8a...89c6da2) --- updated-dependencies: - dependency-name: llvm-project dependency-version: 89c6da2a86e7e4b33867c901a0e78d24b6d2537a dependency-type: direct:production ... Signed-off-by: dependabot[bot] <support@github.com>
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Bumps llvm-project from
6fd5b8ato89c6da2.Commits
89c6da2[AIEX] Move printf declaration under extern "C"d504624[NFC][AIE2PS] Refactor: extract setInsertPtAfterInstr helper in AIECombinerHe...b5bfeaf[AIE2PS] Add combiner to split wide intrinsics for store fusion822b570[AIE2P][AIE2PS] Enable combine_chained_ptradd_with_nonconst as prelegalizer c...0c79888[AIE][AIE2PS] Add postlegalizer combiner for POSTINC memory ops with truncate...1f8859b[AIE][AIE2PS] Extend postlegalizer combiner for chained PTR_ADD with truncate...e35c35a[AIE2PS] Add a new postlegalizer custom (named as final) combiner pass0a4cf9c[AIE2PS][GlobalISel] Fix pointer select legalization to use correct register ...4c4d2fb[AIEX] Add convergence guard for modulo node delay in PostPipeliner9088261[AIEX] Add ExtraStages=0 heuristic and fix modulo node delay logicDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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