GitHub - YashKarthik/uart-icesugar: Implementing UART in Verilog on icesugar fpga

Implementing UART on iCESugar FPGA (Lattice iCE40UP5k).

Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
.clangd		.clangd
.gitignore		.gitignore
.sconsign.dblite		.sconsign.dblite
README.md		README.md
abc.history		abc.history
apio.ini		apio.ini
clock-trace.vcd		clock-trace.vcd
clock.cpp		clock.cpp
clock.v		clock.v
hardware.asc		hardware.asc
hardware.bin		hardware.bin
hardware.json		hardware.json
hardware.out		hardware.out
icesugar.pcf		icesugar.pcf
receiver-trace.vcd		receiver-trace.vcd
receiver.cpp		receiver.cpp
receiver.v		receiver.v
top-trace.vcd		top-trace.vcd
top.cpp		top.cpp
top.v		top.v
transmitter-trace.vcd		transmitter-trace.vcd
transmitter.cpp		transmitter.cpp
transmitter.v		transmitter.v
verilator.f		verilator.f

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