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Pull requests: YosysHQ/nextpnr
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placer_heap: don't lose ripped-up clusters in try_place_cluster
#1779
opened Aug 14, 2026 by
PepperoniPingu
•
Draft
himbaechel/xilinx: don't pair FFs with SRL/LUTRAM on a different clock
#1768
opened Jul 31, 2026 by
0xa000
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himbaechel/xilinx: fix MMCM loop filter and power register programming
#1767
opened Jul 31, 2026 by
0xa000
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himbaechel/xilinx: do not set OUT_DIFF for TMDS_33 outputs
#1766
opened Jul 31, 2026 by
0xa000
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himbaechel/xilinx: fix LUTRAM initialisation (INIT_A..INIT_D)
#1765
opened Jul 31, 2026 by
0xa000
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himbaechel/xilinx: make depth-cascaded RAMB36E1 memories work
#1764
opened Jul 31, 2026 by
0xa000
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add support for FF_OBF merge when Q has multiple sinks or EN is used
gatemate
Cologne Chip CCGM1 (GateMate)
#1742
opened Jun 25, 2026 by
moffel
Contributor
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gatemate: Initial hypergraph partitioner concept
gatemate
Cologne Chip CCGM1 (GateMate)
#1740
opened Jun 19, 2026 by
gatecat
Member
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Add constraint to ignore a net during timing analysis
#1670
opened Mar 15, 2026 by
aWZHY0yQH81uOYvH
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gatemate: input register packing
gatemate
Cologne Chip CCGM1 (GateMate)
#1612
opened Dec 9, 2025 by
Ravenslofty
Collaborator
•
Draft
Avoid throwing out_of_range in log_fmax when related clocks lack Fmax entries
#1600
opened Nov 18, 2025 by
bengtsjolen
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timing: Always split histogram with zero as a boundary
#436
opened Apr 29, 2020 by
smunaut
Contributor
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