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Deleting redundant Verilog code can unexpectedly increase LUT utilization

Status: Open.

#270 In YosysHQ/picorv32;

· xiaguangbo opened on Mar 27, 2025

Synthesis Bug : Mismatch in PCPI INSN and Memory Address

Status: Open.

#269 In YosysHQ/picorv32;

· rsar97 opened on Jan 27, 2025

Is the CPU in PicoRV32 Implemented as a 5-Stage Pipeline?

Status: Open.

#268 In YosysHQ/picorv32;

· alihkousha opened on Dec 15, 2024

Help regarding Simulation of PicoRV32 in vivado

Status: Open.

#267 In YosysHQ/picorv32;

· Tanishqgithub opened on Jul 11, 2024

Fmax and latency on PicoRV32

Status: Open.

#265 In YosysHQ/picorv32;

· SyedFahimuddinAlavi opened on Jul 2, 2024

how to run dhrystone benchmark

Status: Open.

#261 In YosysHQ/picorv32;

· toolchainman opened on May 17, 2024

Dhrystone Floating Extension Problem ?

Status: Open.

#260 In YosysHQ/picorv32;

· drkome opened on May 14, 2024

Verilog HDL Module Instantiation error at hx8kdemo.v(65)

Status: Open.

#259 In YosysHQ/picorv32;

· YapWC opened on Apr 26, 2024

Executing cxxdemo with verilator causing memory out of bound problem:

Status: Open.

#256 In YosysHQ/picorv32;

· SyedFahimuddinAlavi opened on Apr 3, 2024

Issue with branch while using BRAM.

Status: Open.

#251 In YosysHQ/picorv32;

· ashrithaMula opened on Jan 21, 2024

Is this project still maintained?

Status: Open.

#247 In YosysHQ/picorv32;

· lk-davidegironi opened on Nov 16, 2023

wbm_sel_o == 0 during read transactions

Status: Open.

#246 In YosysHQ/picorv32;

· epsilon537 opened on Sep 19, 2023