Yosys 0.66

Yosys 0.65 .. Yosys 0.66

• Various

  • C++ compiler with C++20 support is required.
  • Please be aware that next release will also
    migrate to CMake build system.

• New commands and options

  • Added "lattice_dsp_nexus" pass for Lattice Nexus
    DSP inference.
  • Added "-scopename" option to "synth_gatemate" pass
    that is propagated to "flatten".

Yosys 0.65

Yosys 0.64 .. Yosys 0.65

• New commands and options

  • Added "arith_tree" pass to convert add/sub/macc chains
    to carry-save adder trees.
  • Removed "-force" option from "share" pass.

• Various

  • read_verilog: support positional assignment patterns
    for unpacked arrays.

Yosys 0.64

Yosys 0.63 .. Yosys 0.64

• New commands and options

  • Added "synth_analogdevices" pass to support synthesis
    for Analog Devices FPGAs.

• Various

  • Removed rarely-used options from ABC/ABC9.
    • Removed "-S" option from "abc" pass.
    • Removed "-fast" option from "abc9" and "abc9_exe".
    • Calls to "abc -g AND -fast" to map logic to
      AND-Inverter Graph form should be replaced with
      "aigmap".
    • The above change was made to SBY, so we recommend
      updating it.
  • Added hardware latch support for Gowin FPGAs.

Yosys 0.63

Yosys 0.62 .. Yosys 0.63

• Various

  • Added DSP inference for Gowin GW1N and GW2A.
  • Added support for subtract in preadder for Xilinx arch.
  • Added infrastructure to run a sat solver as a command.

• New commands and options

  • Added "-ignore-unknown-cells" option to "equiv_induct"
    and "equiv_simple" pass.
  • Added "-force-params" option to "memory_libmap" pass.
  • Added "-select-solver" option to "sat" pass.
  • Added "-default_params" option to "write_verilog" pass.
  • Added "-nodsp" option to "synth_gowin" pass.

Yosys 0.62

Yosys 0.61 .. Yosys 0.62

• Various

  • verific: Added "-sv2017" flag option to support System
    Verilog 2017.
  • verific: Added VHDL related flags to "-f" and "-F" and
    support reading VHDL file from file lists.
  • Updated cell libs with proper module declaration where
    non standard (...) style was used.

• New commands and options

  • Added "-word" option to "lut2mux" pass to enable emitting
    word level cells.
  • Added experimental "opt_balance_tree" pass to convert
    cascaded cells into tree of cells to improve timing.
  • Added "-gatesi" option to "write_blif" pass to init gates
    under gates_mode in BLIF format.
  • Added "-on" and "-off" options to "debug" pass for
    persistent debug logging.
  • Added "linux_perf" pass to control performance recording.

Yosys 0.61

Yosys 0.60 .. Yosys 0.61

• Various

  • Removed "cover" pass for coverage tracking.
  • Avoid merging formal properties with "opt_merge" pass.
  • Parallelize "opt_merge" pass.

• New commands and options

  • Added "design_equal" pass to support fuzz-test comparison.
  • Added "lut2bmux" pass to convert $lut to $bmux.
  • Added "-legalize" option to "read_rtlil" pass to prevent
    semantic errors.

Yosys 0.60

Yosys 0.59 .. Yosys 0.60

• Various

  • read_verilog: suport unsized parameters.
  • Added static library compile option.

• New commands and options

  • Added "sdc" pass for reading SDC files.
  • Added experimental "sdc_expand" and "opensta" for OpenSTA integration.
  • Added "icell_liberty" pass for used internal cells.

Yosys 0.59.1

Bugfix release includes:

• pyosys build fixed
• libparse: fix parsing and memory safety of quoted values

Yosys 0.58 .. Yosys 0.59

• Various

  • Pyosys is rewritten using pybind11.
  • alumacc: merge independent of sign.
  • write_btor: Include $assert and $assume cells in -ywmap output.
  • RTLIL parser rewritten for efficiency.
  • Wildcards enabled for Liberty file consuming.
  • timeest: Add top ports launching/sampling.

• New commands and options

  • Added "-apply_derived_type" option to "box_derive" pass.
  • Added "-publish_icells" option to "chtype" pass.
  • Added "-width" option to "sim" pass.
  • Added "sort" pass for sorting the design objects.
  • Merged "synth_ecp5" and "synth_nexus" into "synth_lattice" pass.
  • Added "-strict-gw5a-dffs" and "-setundef" options to "synth_gowin" pass.

Yosys 0.59

Yosys 0.58 .. Yosys 0.59

• Various

  • Pyosys is rewritten using pybind11.
  • alumacc: merge independent of sign.
  • write_btor: Include $assert and $assume cells in -ywmap output.
  • RTLIL parser rewritten for efficiency.
  • Wildcards enabled for Liberty file consuming.
  • timeest: Add top ports launching/sampling.

• New commands and options

  • Added "-apply_derived_type" option to "box_derive" pass.
  • Added "-publish_icells" option to "chtype" pass.
  • Added "-width" option to "sim" pass.
  • Added "sort" pass for sorting the design objects.
  • Merged "synth_ecp5" and "synth_nexus" into "synth_lattice" pass.
  • Added "-strict-gw5a-dffs" and "-setundef" options to "synth_gowin" pass.

Yosys 0.58

Yosys 0.57 .. Yosys 0.58

• Various

  • Run ABC passes in parallel.
  • Extending support for buffer normalization.
  • Overhaul of logging APIs.
  • read_blif: Represent sequential elements with gate cells.
  • Support multiple lib files in abc9_exe.

• New commands and options

  • Added "-wireshape" option to "show" command to allow
    control the shape of wire nodes.
  • Added "-relativeshare" option to "read_verilog", "synth"
    and "techmap" pass for synthesis reproducibility testing.
  • "write_rtlil" pass no longer sorts design, added "-sort"
    option to match old behavior
  • Added "-sva-continue-on-err" to "verific" pass to allow
    processing designs that includes unsupported SVA.