GitHub - YoussefBR/verilog-processor: A CPU from scratch built in verilog using Xilinx Viviado

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A CPU from scratch built in verilog using Xilinx Viviado

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Name		Name	Last commit message	Last commit date
Latest commit History 23 Commits
verilog_processor.cache/wt		verilog_processor.cache/wt
verilog_processor.ip_user_files		verilog_processor.ip_user_files
verilog_processor.runs		verilog_processor.runs
verilog_processor.sim/sim_1/behav/xsim		verilog_processor.sim/sim_1/behav/xsim
verilog_processor.srcs		verilog_processor.srcs
.gitignore		.gitignore
verilog_processor.xpr		verilog_processor.xpr