FPGA Floating-Point Evaluation

This repository contains a generated benchmark report comparing ZKF, FloPoCo, and tomverbeure/math Fpxx floating-point add, multiply, and divide implementations at target-specific clocks. The current report covers Lattice ECP5 using Yosys/nextpnr and Diamond, and AMD/Xilinx Spartan-7 using Vivado.

Published report: https://zubax.github.io/fpga-floating-point-eval/

The committed report is in report/index.html. The root index.html redirects to it for GitHub Pages.

Repository Contents

• report/index.html: generated HTML benchmark report.
• artifacts/targets/: generated synthesis logs, reports, wrappers, and netlists segregated by target/toolchain.
• results.json: structured benchmark summary data.
• scripts/benchmark.py: benchmark generation and reporting script.

Regeneration

Run python3 scripts/benchmark.py full --force to remove generated artifacts and rebuild all targets. The script tunes ZKF staging, FloPoCo generation parameters, and Math Fpxx pipeline/divider table parameters per target, then publishes the selected best timing-closing candidate for each library/operator/format combination. If no candidate closes timing, the report shows the highest-Fmax failing candidate and marks it FAIL.

The Math Fpxx source tree is expected at third_party/math by default, or at $MATH_REPO if set. Verilog generation uses sbt, overridable with $SBT.

Math Fpxx add and multiply candidates are generated with RoundType.ROUNDTOEVEN. Math Fpxx FpxxDiv does not expose a rounding-mode option in the evaluated checkout, so its divider rows use the library's native divider behavior and are not counted as rounding-comparable wins in the report.

Notes

Local toolchains and vendored dependencies are intentionally ignored. Generated report artifacts are checked in so the published report links resolve on GitHub Pages.