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aarushgoradia/README.md

๐Ÿ‘‹ Hi, I'm Aarush

๐ŸŽ“ Rising Junior at Princeton University
๐Ÿ“ Electrical & Computer Engineering | Minors in Computer Science + English


Interests

  • Computer Architecture & Verification
  • High-performance systems and low-level programming
  • Embedded design & digital signal processing
  • AI/ML-powered tooling for hardware workflows

Skills

Languages: C++, Python, Java, C, Verilog, (learning SystemVerilog)
Tools: Cadence Virtuoso/EMX, KiCAD, KLayout, Vivado, NX Siemens

Pinned Loading

  1. riscv-pipelined-core riscv-pipelined-core Public

    SystemVerilog implementation of a 5-stage pipelined RV32I RISC-V core with forwarding, load-use interlock, and branch-flush hazard protection.

    SystemVerilog

  2. 9JAyemi/malik25_26 9JAyemi/malik25_26 Public

    SystemVerilog 1

  3. FixedPointDSP FixedPointDSP Public

    Header-only C++ library for fixed-point arithmetic and basic digital signal processing

    C++ 2

  4. venkatsubra01/GreenCycle venkatsubra01/GreenCycle Public

    HackPrinceton24

    Python 1

  5. memory-pool memory-pool Public

    A minimal C++ memory pool allocator for fixed-size objects, featuring manual and RAII-safe allocation.

    C++ 1

  6. terminal-autocomplete terminal-autocomplete Public

    WIP Machine learning-based CLI tool that autocompletes your terminal commands using your bash history.

    Python 1