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.gitignore
.gitignore
 
 
ALU.v
ALU.v
 
 
FA_dataflow.v
FA_dataflow.v
 
 
README.md
README.md
 
 
README.md~
README.md~
 
 
RegFile.v
RegFile.v
 
 
SCDDataPath.v
SCDDataPath.v
 
 
adder.v
adder.v
 
 
alu_control.v
alu_control.v
 
 
bit32AND.v
bit32AND.v
 
 
bit32OR.v
bit32OR.v
 
 
bit32_3_to_1mux.v
bit32_3_to_1mux.v
 
 
bit8_2to1mux.v
bit8_2to1mux.v
 
 
control_unit.v
control_unit.v
 
 
data_memory.v
data_memory.v
 
 
decoder.v
decoder.v
 
 
decoder2_4.v
decoder2_4.v
 
 
dff_async_clear.v
dff_async_clear.v
 
 
dff_sync_clear.v
dff_sync_clear.v
 
 
fork_join_prac.v
fork_join_prac.v
 
 
full_adder.v
full_adder.v
 
 
instruction_memory.v
instruction_memory.v
 
 
mealy.v
mealy.v
 
 
mealy_test.v
mealy_test.v
 
 
mux16to1.v
mux16to1.v
 
 
mux2to1.v
mux2to1.v
 
 
mux4_1.v
mux4_1.v
 
 
mux4to1.v
mux4to1.v
 
 
regfile32.v
regfile32.v
 
 
register32bit.v
register32bit.v
 
 
register_5bit.v
register_5bit.v
 
 
shift_reg.v
shift_reg.v
 
 
shift_reg_test_bench.v
shift_reg_test_bench.v
 
 
shifter.v
shifter.v
 
 
sign_extender.v
sign_extender.v
 
 
tbALU.v
tbALU.v
 
 
tb_RegFile.v
tb_RegFile.v
 
 
tb_SCD.v
tb_SCD.v
 
 
tb_adder.v
tb_adder.v
 
 
tb_bit32_3_to_1mux.v
tb_bit32_3_to_1mux.v
 
 
tb_multiplexer.v
tb_multiplexer.v
 
 
tb_regfile32.v
tb_regfile32.v
 
 
tb_register32bit.v
tb_register32bit.v
 
 
test_fulladder.v
test_fulladder.v
 
 
testbench.v
testbench.v
 
 
testbench_32bit_mult.v
testbench_32bit_mult.v
 
 
testbenchdff.v
testbenchdff.v
 
 
testmux_16.v
testmux_16.v
 
 

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Single Cycle Data Implementation in Verilog

This repository contains some of the solutions of the labsheets.

Single Cycle Datapath was attempted.

Main file is SCDDataPath.v, and its testbench is in tb_SCD.v. For now instruction memory is loaded with R instrutions. Few components are left to support jump and branch instruction.

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