absl/crc: Add RISC-V hardware acceleration for CRC32C #1986
+299
−2
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Description
This PR introduces a hardware-accelerated implementation of CRC32C for RISC-V processors that support the
ZbcorZbkcextensions.Motivation
CRC32C is a performance-critical operation in many applications. The current software fallback on RISC-V is slower than what can be achieved using the carry-less multiplication instructions available in the
Zbcextension. This change leverages these instructions to improve throughput.Changes
absl/crc/internal/crc_riscv.cc: ImplementedAbslCrc32cClmulRiscvusingclmulandclmulhinstructions via inline assembly. The implementation uses a folding approach similar to the x86/ARM combined implementation.absl/crc/internal/cpu_detect.cc: Added runtime CPU feature detection for RISC-V usingriscv_hwprobeon Linux to safely enable the accelerated path only when the hardware supports it.absl/crc/internal/crc.cc: UpdatedCRCImpl::NewInternalto instantiate the RISC-V implementation when supported hardware is detected.CMakeLists.txtto detect compiler support for-march=rv64gc_zbcor-march=rv64gc_zbkcand apply it to the specific translation unit.BUILD.bazelto apply-march=rv64gc_zbcforriscv64builds using GCC/Clang.Performance
Benchmarks were run on a RISC-V 64-bit system (64 cores @ 2.6GHz).
Benchmark:
//absl/crc:crc32c_benchmarkBM_Calculate/500000BM_Extend/500000BM_Extend/100000000BM_ExtendCacheMiss/100000Throughput (MiB/s)
BM_ExtendCacheMiss/100BM_ExtendCacheMiss/1000BM_ExtendCacheMiss/100000Testing
Ran
//absl/crc:alltests on the target hardware.All 231 tests in the project passed.
Raw Benchmark Data (Origin)
Raw Benchmark Data (Patch)