Verilog/jk_latch.v at main · adityasmalagi/Verilog · GitHub

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`timescale 1ns / 1ps

module jk_latch(
    input rst,enb,j,k,output reg q,qbar
    );

    always@(enb,rst)begin
            if(rst)
                begin
             q <= 1'b0;
             qbar <= 1'b1;
             end

             if(enb)
                begin
                if(j == 0 && k == 0)begin
                q <= q;
                qbar <= qbar;
                end

             else if(j == 0 && k == 1)begin
                q <= 1'b0;
                qbar <= 1'b1;
                end

              else if(j == 1 && k == 0)begin
                 q <= 1'b1;
                 qbar <= 1'b0;
                 end
              else if(j == 1 && k == 1)begin
                 q <= ~q;
                 qbar <= ~qbar;
                 end
          end
      end
endmodule