[Bugfix][MoE][XPU] Gate topk_id=-1 padding sentinel on XPU (stopgap for vllm-xpu-kernels#572) - #71
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`VLLM_MOE_SKIP_PADDING` (on by default) makes the fused top-k routers write `topk_id = -1` for padding rows, and relies on the MoE kernels treating that as a skip sentinel. The SYCL `moe_align_block_size` in vllm-xpu-kernels only rejects `expert_id >= num_experts`; it is missing the `expert_id < 0` half that the CUDA kernel gained in vllm-project#47785. On XPU the sentinel is therefore used as an index: `cumsum_buffer[-1]` is atomically incremented once per padding entry, and `_count_and_sort_expert_tokens` writes token indices at the resulting arbitrary offset past `sorted_token_ids`. The V2 model runner's profile run marks every row as padding, so the very first MoE forward emits `topk_ids` that are entirely -1 and the stray write covers `topk_ids.numel()` int32s. Depending on where that lands, the result is either silently corrupted fp16 weights in the neighbouring caching- allocator small-pool segment (MoE router gates included, i.e. incoherent output for the whole server lifetime) or a native segfault during startup. Gate the sentinel behind a new platform capability instead of the env var alone, and opt XPU out. Fixing the guard in the SYCL kernel is the real fix and is being handled in vllm-xpu-kernels; this keeps vLLM from feeding a kernel input it cannot handle in the meantime. Reproducer: Qwen/Qwen1.5-MoE-A2.7B-Chat-GPTQ-Int4 on Arc Pro B60, TP=1, fp16, `--quantization moe_wna16 --moe-backend triton` (TritonWNA16Experts). Before: segfault in the profile run, 100% of runs. After: coherent output, 3/3 runs; `--moe-backend auto` (XPUExpertsWNA16) unaffected either way. Assisted-by: Claude Opus 5 (Claude Code) Signed-off-by: Artur Fierka <artur.fierka@intel.com>
…l gate - Drop the @functools.cache on the padding-sentinel check: caching a platform-capability + env-var read is unsafe across tests/platforms that monkeypatch either one at runtime. - Consolidate the duplicated skip-padding helper (previously copy-pasted in fused_topk_router.py and fused_topk_bias_router.py) into a single base_router.get_padding_mask(), imported by both. - Add a device-agnostic unit test covering all four gate outcomes (env off, platform unsupported, no forward context, mask returned). - Broaden the XPU comment and the interface.py docstring: the exposure also covers moe_align_block_size's small-batch-expert variant, which has no bound check at all (not just the missing `< 0` guard on the large-batch path this PR was validated against). Co-authored-by: Claude Sonnet 5 <noreply@anthropic.com> Signed-off-by: Artur Fierka <artur.fierka@intel.com>
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Superseded — published upstream as vllm-project#55231. |
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What
New
Platform.supports_moe_padding_sentinel()(defaultTrue). XPU overrides toFalse; both top-k routers gatetopk_id = -1emission on it instead of the rawVLLM_MOE_SKIP_PADDINGenv var. Check consolidated intobase_router.get_padding_mask()(no@functools.cache— caching a platform+env check is unsafe under monkeypatching).Why — stopgap for vllm-xpu-kernels#572, not a permanent fix
SYCL
moe_align_block_sizenever gained theexpert_id < 0guard CUDA has.topk_id = -1(padding sentinel, emitted wheneverVLLM_MOE_SKIP_PADDINGis on — default) is used as a raw index, writing out of bounds in_count_and_sort_expert_tokensand the small-batch-expert path. Depending on overflow size: silent weight corruption or device crash. Not WNA16-specific — any Triton MoE on XPU going through this kernel is exposed.The real fix is vllm-project/vllm-xpu-kernels#572 (adds the guard at all 4 unguarded sites). This PR is a temporary shield for
vllm-xpu-kernelsbuilds that predate vllm-project#572 — remove it once vllm-project#572 ships in a released wheel thatrequirements/xpu.txtpins.Not a duplicate: vllm-project#50759 covers routers without native padding support (different gap); vllm-project#42034 fixes the same "-1 as index" hazard in FlashInfer NVLink EP dispatch (different, CUDA-only path).
Test plan
4 passed, device-agnostic — also passed against a real CUDA platform (see below).Hardware (Intel B60, TP=1/TP=2), unpatched vs. patched:
moe_wna16,--moe-backend triton--moe-backend triton(genericTritonExperts)DEVICE_LOSTinprofile_run()Native SYCL (
--moe-backend auto, nomoe_align_block_sizecall) hits an unrelatedptr_A.size(1)≠ptr_B.size(1)bug identically with and without this patch — separate, pre-existing, not fixed here.CUDA (L40S): this diff
patch -p1'd onto stockvllm-openai:0.28.0— generation output byte-identical unpatched vs. patched, unit tests pass against the realCudaPlatform. No cross-platform regression.AI-assisted (Claude Code / Opus); I reviewed every changed line and reproduced all results above myself.