feat: add foundational RISC-V and RVV support infrastructure - #311
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feat: add foundational RISC-V and RVV support infrastructure#311ihb2032 wants to merge 8 commits into
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ihb2032
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Signed-off-by: ihb2032 <hebome@foxmail.com>
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Conflict resolution policy: keep upstream (main) for shared code, retain this branch's changes only for RISC-V/RVV-related parts. - src/ailego/CMakeLists.txt: keep upstream's restructured per-arch per-file march block (incl. MSVC ARM64 NEON comment); re-add the riscv64 *_rvv.cc glob with setup_compiler_march_for_riscv64_rvv(). - src/ailego/internal/cpu_features.cc: keep upstream's includes and simplified compiler guards; retain the riscv_hwprobe-based runtime detection (RISCV_VECTOR/RISCV_ZVFH) and the riscv CpuFlags ctor. - src/include/zvec/ailego/internal/platform.h: keep upstream's AILEGO_ARM64/AILEGO_HAVE_NEON structure; retain riscv64 in AILEGO_M64, riscv_vector.h include, zihintpause ailego_yield, and the __riscv_vector tier in ailego_malloc. - src/ailego/internal/cpu_features.h: drop stale conflict markers committed earlier; keep both NEON (upstream) and the new RISCV_VECTOR/RISCV_ZVFH static flags.
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Motivation & Context
This PR introduces the fundamental infrastructure required to support the RISC-V 64-bit architecture and the RISC-V Vector Extension.
Adding this underlying scaffolding paves the way for significant performance optimizations. Preliminary downstream testing with RVV intrinsics has already demonstrated massive potential, including nearly 9x QPS improvements in int8 workloads without any drop in recall. This PR is the necessary first step to upstream those gains safely and cleanly.
Performance Context:
What's Next?
This is part 1 of a planned series of PRs. Once this foundational PR is merged, follow-up PRs will introduce the actual algorithmic optimizations that utilize these new
cpu_featuresAPIs.Testing Performed