This project presents the design and implementation of a single-cycle MIPS 32-bit CPU using Logisim-evolution simulation software. The objective was to develop a functional processor capable of executing core MIPS instructions while demonstrating key computer architecture principles. The implementation includes essential components such as an Arithmetic Logic Unit (ALU), register file, control unit, program counter, and memory modules, all integrated into a cohesive datapath system.
The CPU successfully executes R-type instructions (ADD, SUB, AND, OR, XOR, SLT, SLL, SRL), I-type instructions (ADDI, LW, SW, BEQ, BNE), and J-type instructions (J, JAL). A systematic testing approach verified proper operation across various instruction sequences. The project demonstrates a practical application of MIPS architecture principles while providing valuable insights into CPU design methodologies.