Attributes of 2 signals are merged if they're driven by the same source

[jorolf]

In the following code, DUT.first and DUT.second are separate signals. They are assigned different attributes:

from amaranth import *
from amaranth.back import rtlil, verilog
import amaranth_playground
from amaranth.lib import wiring


class DUT(wiring.Component):
    first: wiring.Out(1)
    second: wiring.Out(1)

    def elaborate(self, _platform):
        m = Module()

        self.first.attrs["foo"] = "first"
        m.d.comb += self.first.eq(0)

        self.second.attrs["bar"] = "second"
        m.d.comb += self.second.eq(0)

        return m
    

dut = DUT()

amaranth_playground.show_verilog(verilog.convert(dut))
amaranth_playground.show_rtlil(rtlil.convert(dut))

Playground Link

However in the resulting rtlil their attributes are merged:

attribute \generator "Amaranth"
attribute \src "<exec>:12"
attribute \top 1
module \top

  attribute \src "<exec>:9"
  attribute \foo "first"
  attribute \bar "second"
  wire width 1 output 0  \first

  attribute \src "<exec>:9"
  attribute \foo "first"
  attribute \bar "second"
  wire width 1 output 1  \second

connect \first 1'0
connect \second 1'0

end

This is especially frustrating when both signals use the same attribute key, leading to one overwriting the other. If you change the driving value of only one signal, the attributes are split again.