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Certain graph shapes can cause simulation to take exponential time

bug

Status: Open.

#1659 In amaranth-lang/amaranth;

· psmears opened on Mar 18, 2026

Add a diagnostic on foo: In(1) being typo'd as foo: 1

improvement

Status: Open.

#1649 In amaranth-lang/amaranth;

· whitequark opened on Dec 29, 2025

Invalid verilog generated on exhaustive switch statements with assert in default clause

bug

toolchain:yosys

upstream

Status: Open.

#1648 In amaranth-lang/amaranth;

· qbojj opened on Dec 29, 2025

Update installation instructions to account for externally-managed-environment

Status: Open.

#1641 In amaranth-lang/amaranth;

· whitequark opened on Dec 2, 2025

Tracking issue for RFC 78: Internal I/O ports

improvement

Status: Open.

#1639 In amaranth-lang/amaranth;

· wanda-phi opened on Dec 1, 2025

Tighter bounds for integer negation of 1-bit signals

feature

meta:needs-rfc

Status: Open.

#1631 In amaranth-lang/amaranth;

· CatsAreFluffy opened on Oct 8, 2025

Pysim performance dependent on module structure

question

simulator:pysim

Status: Open.

#1630 In amaranth-lang/amaranth;

· tilk opened on Sep 22, 2025

If/Else for combinational assignment generates always @* that doesn't initialize

backend:verilog

bug

upstream

Status: Open.

#1629 In amaranth-lang/amaranth;

· epkRichi opened on Sep 19, 2025

Memory read port data uninitialized and not resettable

backend:rtlil

bug

Status: Open.

#1625 In amaranth-lang/amaranth;

· epkRichi opened on Aug 8, 2025

Spaces in names generates invalid RTLIL

bug

Status: Open.

#1622 In amaranth-lang/amaranth;

· rroohhh opened on Jul 30, 2025

Tracking issue for RFC 80: Simulation task groups

feature

Status: Open.

#1620 In amaranth-lang/amaranth;

· zyp opened on Jul 28, 2025

Attributes of 2 signals are merged if they're driven by the same source

backend:rtlil

bug

Status: Open.

#1616 In amaranth-lang/amaranth;

· jorolf opened on Jul 16, 2025