agregate Signal()

[jalcim]

My question is, how can we make a "Signal(2)" with 2 "Signal(1)"

EXEMPLE :

first = Signal(1)
second = Signal(1)
third = first + second

CONTEXT :
inside a class Module()

we have :

definition of param

self.params = {
                "i_in" : am.Signal(2),
                "o_out": am.Signal(1),
            }

instanciate Verilog_module

self.module = Verilog_module(
            "gate_and",
            **self.params
        )

now i want to take the output of 2 gate_and (verilog module),
for plug on input of a third gate_and.

For that how can we do ? did we need to agregate the am.Signal() returned in "o_out" ?

here a schematic.

[whitequark]

Try this:

first = Signal(1)
second = Signal(1)
Cat(first, second)