library/spi_engine: fix transfer counter condition (#1654)

fix bug where for a clock divider of 0, multi-word transfers
could hang without ever completing

Signed-off-by: Laez Barbosa <[email protected]>

Author: LBFFilho

docs/regmap/adi_regmap_spi_engine.txt

@@ -25,7 +25,7 @@ RO
 ENDFIELD
 
 FIELD
-[7:0] 0x00000002
+[7:0] 0x00000003
 VERSION_PATCH
 RO
 ENDFIELD

library/spi_engine/spi_engine_execution/spi_engine_execution.v

@@ -316,7 +316,7 @@ module spi_engine_execution #(
       ntx_rx  <= 1'b0;
       sleep_counter_increment <= 1'b0;
     end else if (clk_div_last == 1'b1 && wait_for_io == 1'b0) begin
-      if (bit_counter == word_length && transfer_active) begin
+      if (last_bit && transfer_active && ntx_rx) begin
         bit_counter <= 'h0;
         transfer_counter <= transfer_counter + 1;
         ntx_rx <= ~ntx_rx;