Madura add orx #2923
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| // SPDX-License-Identifier: GPL-2.0 | ||
| /* | ||
| * Analog Devices ADRV9025 | ||
| * https://wiki.analog.com/resources/eval/user-guides/adrv9025 | ||
| * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/adrv9025 | ||
| * | ||
| * hdl_project: <adrv9026/zcu102> | ||
| * board_revision: <> | ||
| * | ||
| * Copyright (C) 2020-2025 Analog Devices Inc. | ||
| */ | ||
| #include "zynqmp-zcu102-rev10-adrv9025.dts" | ||
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| &trx0_adrv9025 { | ||
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| clock-output-names = "rx_sampl_clk", "tx_sampl_clk", "rx_os_sampl_clk"; | ||
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| adi,device-profile-name = "ActiveUseCase_NLS.profile"; | ||
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| jesd204-device; | ||
| #jesd204-cells = <2>; | ||
| jesd204-top-device = <0>; /* This is the TOP device */ | ||
| jesd204-link-ids = <DEFRAMER0_LINK_TX FRAMER0_LINK_RX FRAMER1_LINK_RX>; | ||
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| jesd204-inputs = | ||
| <&axi_adrv9025_rx_jesd 0 FRAMER0_LINK_RX>, | ||
| <&axi_adrv9025_rx_os_jesd 0 FRAMER1_LINK_RX>, | ||
| <&axi_adrv9025_core_tx 0 DEFRAMER0_LINK_TX>; | ||
| }; | ||
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| &fpga_axi { | ||
| rx_os_dma: dma@9c800000 { | ||
| compatible = "adi,axi-dmac-1.00.a"; | ||
| reg = <0x9c800000 0x10000>; | ||
| #dma-cells = <1>; | ||
| #clock-cells = <0>; | ||
| dma-coherent; | ||
| interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; | ||
| clocks = <&zynqmp_clk 73>; | ||
| }; | ||
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| axi_rx_os_clkgen: axi-clkgen@83c20000 { | ||
| compatible = "adi,axi-clkgen-2.00.a"; | ||
| reg = <0x83c20000 0x10000>; | ||
| #clock-cells = <0>; | ||
| clocks = <&clk0_ad9528 3>, <&zynqmp_clk 71>; | ||
| clock-names = "clkin1", "s_axi_aclk"; | ||
| clock-output-names = "axi_rx_os_clkgen"; | ||
| }; | ||
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| axi_adrv9025_core_rx_os: axi-adrv9025-rx-os-hpc@84a08000 { | ||
| compatible = "adi,axi-adrv9025-obs-1.0"; | ||
| reg = <0x84a08000 0x8000>; | ||
| dmas = <&rx_os_dma 0>; | ||
| dma-names = "rx"; | ||
| clocks = <&trx0_adrv9025 2>; | ||
| clock-names = "sampl_clk"; | ||
| spibus-connected=<&trx0_adrv9025>; | ||
| label="axi-adrv9025-rx-os-hpc"; | ||
| }; | ||
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| axi_adrv9025_rx_os_jesd: axi-jesd204-rx-os@85aa0000 { | ||
| compatible = "adi,axi-jesd204-rx-1.0"; | ||
| reg = <0x85aa0000 0x1000>; | ||
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| interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | ||
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| clocks = <&zynqmp_clk 71>, <&axi_rx_os_clkgen>, <&axi_adrv9025_adxcvr_rx_os 0>; | ||
| clock-names = "s_axi_aclk", "device_clk", "lane_clk"; | ||
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| #clock-cells = <0>; | ||
| clock-output-names = "jesd_rx_os_lane_clk"; | ||
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| adi,octets-per-frame = <4>; | ||
| adi,frames-per-multiframe = <32>; | ||
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| jesd204-device; | ||
| #jesd204-cells = <2>; | ||
| jesd204-inputs = <&axi_adrv9025_adxcvr_rx_os 0 FRAMER1_LINK_RX>; | ||
| }; | ||
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| axi_adrv9025_adxcvr_rx_os: axi-adxcvr-rx-os@85a60000 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| compatible = "adi,axi-adxcvr-1.0"; | ||
| reg = <0x85a60000 0x1000>; | ||
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| clocks = <&clk0_ad9528 13>; | ||
| clock-names = "conv"; | ||
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| #clock-cells = <1>; | ||
| clock-output-names = "rx_os_gt_clk", "rx_os_out_clk"; | ||
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| adi,sys-clk-select = <XCVR_CPLL>; | ||
| adi,out-clk-select = <XCVR_REFCLK>; | ||
| adi,use-lpm-enable; | ||
| adi,use-cpll-enable; | ||
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| jesd204-device; | ||
| #jesd204-cells = <2>; | ||
| jesd204-inputs = <&clk0_ad9528 0 FRAMER1_LINK_RX>; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,102 @@ | ||
| // SPDX-License-Identifier: GPL-2.0 | ||
| /* | ||
| * Analog Devices ADRV9025 | ||
| * https://wiki.analog.com/resources/eval/user-guides/adrv9025 | ||
| * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/adrv9025 | ||
| * | ||
| * hdl_project: <adrv9026/zcu102> | ||
| * board_revision: <> | ||
| * | ||
| * Copyright (C) 2020-2025 Analog Devices Inc. | ||
| */ | ||
| #include "vcu118_adrv9025.dts" | ||
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| &trx0_adrv9025 { | ||
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| clock-output-names = "rx_sampl_clk", "tx_sampl_clk", "rx_os_sampl_clk"; | ||
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| jesd204-device; | ||
| #jesd204-cells = <2>; | ||
| jesd204-top-device = <0>; /* This is the TOP device */ | ||
| jesd204-link-ids = <DEFRAMER0_LINK_TX FRAMER0_LINK_RX FRAMER1_LINK_RX>; | ||
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| jesd204-inputs = | ||
| <&axi_adrv9025_rx_jesd 0 FRAMER0_LINK_RX>, | ||
| <&axi_adrv9025_rx_os_jesd 0 FRAMER1_LINK_RX>, | ||
| <&axi_adrv9025_core_tx 0 DEFRAMER0_LINK_TX>; | ||
| }; | ||
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| &amba_pl { | ||
| rx_os_dma: dma@7c800000 { | ||
| compatible = "adi,axi-dmac-1.00.a"; | ||
| reg = <0x7c800000 0x10000>; | ||
| #dma-cells = <1>; | ||
| #clock-cells = <0>; | ||
| interrupt-parent = <&axi_intc>; | ||
| interrupts = <14 2>; | ||
| clocks = <&clk_bus_0>; | ||
| }; | ||
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| axi_rx_os_clkgen: axi-clkgen@43c20000 { | ||
| compatible = "adi,axi-clkgen-2.00.a"; | ||
| reg = <0x43c20000 0x10000>; | ||
| #clock-cells = <0>; | ||
| clocks = <&clk0_ad9528 3>, <&clk_bus_0>; | ||
| clock-names = "clkin1", "s_axi_aclk"; | ||
| clock-output-names = "axi_rx_os_clkgen"; | ||
| }; | ||
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| axi_adrv9025_core_rx_os: axi-adrv9025-rx-os-hpc@44a08000 { | ||
| compatible = "adi,axi-adrv9025-obs-1.0"; | ||
| reg = <0x44a08000 0x8000>; | ||
| dmas = <&rx_os_dma 0>; | ||
| dma-names = "rx"; | ||
| clocks = <&trx0_adrv9025 2>; | ||
| clock-names = "sampl_clk"; | ||
| spibus-connected=<&trx0_adrv9025>; | ||
| label="axi-adrv9025-rx-os-hpc"; | ||
| }; | ||
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| axi_adrv9025_rx_os_jesd: axi-jesd204-rx-os@45aa0000 { | ||
| compatible = "adi,axi-jesd204-rx-1.0"; | ||
| reg = <0x45aa0000 0x1000>; | ||
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| interrupt-parent = <&axi_intc>; | ||
| interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; | ||
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| clocks = <&clk_bus_0>, <&axi_rx_os_clkgen>, <&axi_adrv9025_adxcvr_rx_os 0>; | ||
| clock-names = "s_axi_aclk", "device_clk", "lane_clk"; | ||
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| #clock-cells = <0>; | ||
| clock-output-names = "jesd_rx_os_lane_clk"; | ||
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| adi,octets-per-frame = <4>; | ||
| adi,frames-per-multiframe = <32>; | ||
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| jesd204-device; | ||
| #jesd204-cells = <2>; | ||
| jesd204-inputs = <&axi_adrv9025_adxcvr_rx_os 0 FRAMER1_LINK_RX>; | ||
| }; | ||
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| axi_adrv9025_adxcvr_rx_os: axi-adxcvr-rx-os@45a60000 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| compatible = "adi,axi-adxcvr-1.0"; | ||
| reg = <0x45a60000 0x1000>; | ||
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| clocks = <&clk0_ad9528 13>; | ||
| clock-names = "conv"; | ||
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| #clock-cells = <1>; | ||
| clock-output-names = "rx_os_gt_clk", "rx_os_out_clk"; | ||
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| adi,sys-clk-select = <XCVR_CPLL>; | ||
| adi,out-clk-select = <XCVR_REFCLK>; | ||
| adi,use-lpm-enable; | ||
| adi,use-cpll-enable; | ||
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| jesd204-device; | ||
| #jesd204-cells = <2>; | ||
| jesd204-inputs = <&clk0_ad9528 0 FRAMER1_LINK_RX>; | ||
| }; | ||
| }; | ||
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Ah I failed to realize this... Being nitpicky, the microblaze DT should be in a separate patch. Anyways, just a hint for the future. No need to change it if there isn't a stronger reason for you to re-spin.