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This syncs the clk-axi-clkgen with linux before our out of tree changes were added there. Thus, it makes cherry picking those commits easier. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
In order to access the registers of the HW, we need to make sure that the AXI bus clock is enabled. Hence let's increase the number of clocks by one. In order to keep backward compatibility and make sure old DTs still work we check if clock-names is available or not. If it is, then we can disambiguate between really having the AXI clock or a parent clock and so we can enable the bus clock. If not, we fallback to what was done before and don't explicitly enable the AXI bus clock. Note that if clock-names is given, the axi clock must be the last one in the phandle array (also enforced in the DT bindings) so that we can reuse as much code as possible. Fixes: 0e646c5 ("clk: Add axi-clkgen driver") Signed-off-by: Nuno Sa <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20241029-axi-clkgen-fix-axiclk-v2-2-bc5e0733ad76@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The fpfd_max frequency should be set to 450 MHz instead of 300 MHz. Well, it actually depends on the platform speed grade but we are being conservative for ultrascale so let's be consistent. In a following change we will set these limits at runtime. Fixes: 0e646c5 ("clk: Add axi-clkgen driver") Signed-off-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20250519-dev-axi-clkgen-limits-v6-1-bc4b3b61d1d4@analog.com Reviewed-by: David Lechner <dlechner@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The mod_devicetable header is the one to be used for struct of_device_id. Signed-off-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20250519-dev-axi-clkgen-limits-v6-2-bc4b3b61d1d4@analog.com Reviewed-by: David Lechner <dlechner@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The adi-axi-common.h header has some common defines used in various ADI IPs. However they are not specific for any fpga manager so it's questionable for the header to live under include/linux/fpga. Hence let's just move one directory up and update all users. [NS] Adapt our out of tree drivers and drop not used defines. Suggested-by: Xu Yilun <yilun.xu@linux.intel.com> Acked-by: Xu Yilun <yilun.xu@intel.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # for IIO Signed-off-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20250519-dev-axi-clkgen-limits-v6-3-bc4b3b61d1d4@analog.com Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Uwe Kleine-König <ukleinek@kernel.org> Reviewed-by: David Lechner <dlechner@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This patch adds support for setting the limits in struct axi_clkgen_limits in accordance with fpga speed grade, voltage, technology and family. This new information is extracted from two new registers implemented in the ip core that are only available for core versions higher or equal to 4. Signed-off-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20250519-dev-axi-clkgen-limits-v6-5-bc4b3b61d1d4@analog.com Reviewed-by: David Lechner <dlechner@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Instead of using the type versions of min/max(), use the plain ones as now they are perfectly capable of handling different types like unsigned and non negative integers that are compiletime constant. Signed-off-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20250519-dev-axi-clkgen-limits-v6-6-bc4b3b61d1d4@analog.com Reviewed-by: David Lechner <dlechner@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This is just cosmetics and so no functional changes intended. While at it, sort header in alphabetical order. Signed-off-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20250519-dev-axi-clkgen-limits-v6-7-bc4b3b61d1d4@analog.com Reviewed-by: David Lechner <dlechner@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
With the change backported from upstream, the AXI bus clock needs to be the last one given in DT. Hence, update accordingly. Note that for zynq, given that the parent is the same as the AXI clock it would not matter much but better be consistent. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
With the change backported from upstream, the AXI bus clock needs to be the last one given in DT. Hence, update accordingly. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
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PR Description
The out of tree changes we had in that driver were upstreamed (in a different manner) so backport them so that this driver is in sync with upstream.
As done for other parts, we first remove the out of tree changes so that it's easier to cherry pick the upstream patches.
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