Commit 032cc1e
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ci: upload hw-test DTS/DTB/dmesg outputs as workflow artifacts
Hardware failures on the hw-coord (mini2) leg are now real test-code
bugs surfaced by CI (AD9081 JESD PLL lock failure on the System-API
path where the XSA path works), but debugging them blind from the
pytest tail is slow. Attach `actions/upload-artifact@v4` steps to
both hw-direct and hw-coord that capture, per matrix leg, the
relevant artefacts under `test/hw/output/`:
- Generated `*.dts` / `*.pp.dts` (pre-dtc, after cpp)
- Compiled `*.dtb` / `*.dtbo`
- `dmesg_*.log` from the booted board
- Any `uart_log_*.txt` produced by `BootFPGASoC.debug_write_boot_log`
when a boot stage times out
Uploaded with `if: always()` so failed runs attach outputs too.
Retention-days = 14 so they don't pile up. Lets us diff the XSA vs
System-API DTS locally to pinpoint the remaining JESD-PLL gap.1 parent 7f991f1 commit 032cc1e
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