Commit 945b954
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fix(ad9081): mode-table M/F now match the jesd204b mode-10/9 reality
The ADC (jtx) mode 10 jesd204b and DAC (jrx) mode 9 jesd204b entries
in ``_AD9081_{RX,TX}_MODE_TABLE`` were set to ``M=4``, but the
AD9081 API mode table and the stock Kuiper
``zynqmp-zcu102-rev10-ad9081-m8-l4`` reference DTS both set ``M=8``
for those modes. The XSA path emits ``converters-per-device = <8>``
because it sources framing straight from the pyadi-jif solver
(which asks for ``M=8, L=4`` and returns mode 10/9) — so the XSA
hw test works.
The System-API path goes through ``ConverterSide.set_jesd204_mode``
which filled framing from our mode table, so ``converters-per-device``
came out ``<4>``. On hardware the kernel AD9081 driver then
programmed the TPL + ADXCVR for fewer converters than the part's
jtx actually frames, and the JESD PLL never locked
("ad9081 ...: JESD PLL is not locked. Failed to initialize: -24").
Correct both table entries to ``M=8, L=4, F=4``. RX mode 10's
``F=2`` was also wrong — the reference DTS and the XSA solver both
use ``octets-per-frame = <4>``, so the ADC's 4-octet framing now
matches.
Unit tests still pass (no fixed-M=4 expectation anywhere).1 parent 032cc1e commit 945b954
1 file changed
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