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Added more ARMCortexM registers #356

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Merged
ltfish merged 1 commit into from
Jul 1, 2026
Merged

Added more ARMCortexM registers #356

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5 changes: 4 additions & 1 deletion archinfo/arch_arm.py
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Original file line number Diff line number Diff line change
Expand Up @@ -446,7 +446,9 @@ class ArchARMCortexM(ArchARMEL):
Register(name="msplim", size=4, general_purpose=True),
Register(name="msplim_s", size=4, general_purpose=True),
Register(name="msplim_ns", size=4, general_purpose=True),
Register(name="msplim_ns", size=4, general_purpose=True),
Register(name="psplim", size=4, general_purpose=True),
Register(name="psplim_s", size=4, general_purpose=True),
Register(name="psplim_ns", size=4, general_purpose=True),
# additional stack pointers for secure/non_secure world
Register(name="sp_process", size=4, general_purpose=True),
Register(name="sp_process_s", size=4, general_purpose=True),
Expand Down Expand Up @@ -507,6 +509,7 @@ class ArchARMCortexM(ArchARMEL):
# Bit 1: Whether we use MSP (0) or PSP (1)
# Bit 0: Thread mode privilege level. 0 for privileged, 1 for unprivileged.
Register(name="control", size=4, default_value=(0, False, None)),
Register(name="control_ns", size=4, default_value=(0, False, None)),
]

# Special handling of CM mode in *stone
Expand Down
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