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STM32H7: set ADC PLL clock for various source configurations#29

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facchinm wants to merge 1 commit intoextrapatches-6.16.0from
adc_fix_stm32h7
Open

STM32H7: set ADC PLL clock for various source configurations#29
facchinm wants to merge 1 commit intoextrapatches-6.16.0from
adc_fix_stm32h7

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@facchinm
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@facchinm facchinm commented Dec 5, 2022

Replaces c65d254

Summary of changes

Impact of changes

Migration actions required

Documentation


Pull request type

[] Patch update (Bug fix / Target update / Docs update / Test update / Refactor)
[] Feature update (New feature / Functionality change / New API)
[] Major update (Breaking change E.g. Return code change / API behaviour change)

Test results

[] No Tests required for this change (E.g docs only update)
[] Covered by existing mbed-os tests (Greentea or Unittest)
[] Tests / results supplied as part of this PR

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@facchinm
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facchinm commented Dec 5, 2022

@manchoz can you give it a spin on x8 / h7 ?

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manchoz commented Dec 19, 2022

@facchinm LGTM 👍

Tested both with X8 and H7 with Portenta Breakout Carrier.

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CLAassistant commented Mar 18, 2026

CLA assistant check
All committers have signed the CLA.

@arduino arduino deleted a comment from CLAassistant Mar 23, 2026
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3 participants